[SI-LIST] Re: DDR SDRAM signal routing
- From: Ray Anderson <reanderson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 08 Nov 2004 07:28:38 -0800
Peter Müller wrote:
>I have been designing different kinds of electronic products, but never a
>DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb chip, 8-bit @
>167MHz)and 2 ECC chips (same type).
>
>Between the processor (IBM PowerPC 440GX) and memory chips there are only
>the transmission lines and series termination resistors (25Ohm close to the
>processor). I do not have the possibility to run simulations, so it's
>learning by doing.
>
>
>
You mentioned that you don't have the "possibility to run simulations".
I would submit that it is almost mandatory to simulate complex,
high-speed interfaces prior to committing a design to fab if you don't
want to go thru multiple iterations of the board prior to finding a
topology that works well (if at all). The cost of simulating (and there
are some low or no cost solutions) is much less than the costs you'll
incur with the 'cut and try' approach.
App-notes and rules of thumb will only get you pointed in the right
direction, but I feel simulation is the real key to understanding what
is happening in any particular design (assuming the design is modeled
correctly).
-Ray Anderson
Senior Signal Integrity Staff Engineer
Xilinx Inc.
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