If I may add my two cents, this solution is fine if the controller is standard. Some FPGAs (IP) vendors use retiming ( a 4x or 2x clock) to register the data. In this situation, DQ must meet certain tsu and th, which a function of the clock. /dan --- "Moran, Brian P" <brian.p.moran@xxxxxxxxx> wrote: > Peter, > > There are of course numerous timing paths on a DDR2 > interface. The > primary paths associated with the data bus are DQ to > DQS setup and hold > margins, and the DQS to CLK setup and hold margins. > The DQ to DQS timing > is often discussed in terms of DQ to DQS skew, and > is measured within > each byte lane independently. To maximize these > margins it is necessary > to match each of the DQ signals to there associated > DQS strobe, on a > byte lane by byte lane basis. (In some cases there > may be a fixed offset > specified between DQ and DQS in order to center the > setup and hold > margins.) The overall length of the byte lane has > only a second order > impact on these calculations. The length range over > which each byte lane > may be routed as a group is usually fairly wide.=20 > > > The amount of length range over which the byte lanes > may vary is > controlled by the DQS to CLK path, for the most > part. Here you have to > worry about traditional setup and hold with respect > to the clock. In > this case the longest DQS signal will generally > control setup margin and > the shortest DQS will control hold margin. > > If you look at Intel guidelines for example, there > is a spec for DQ to > DQS length matching within a byte lane, which is > generally on the order > of DQ length =3D (DQS Length - Offset) +/-20 mils. > Then there is a > guideline for DQS vs CLK length matching which may > be on the order of > CLK - 2.0" </=3D DQS </=3D CLK + 1.0". This is just > an example and you = > need > to consult the guidelines provided by your > controller vendor, but this > is how the guidelines are generally structured. > > > Brian P. Moran=20 > SIE Engineer=20 > Intel Corporation=20 > brian.p.moran@xxxxxxxxx=20 > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx > [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of peter zhu > Sent: Friday, November 26, 2004 3:04 AM > To: si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] SDRAM timing > > Hi, all: > > I oftem see designer reel the PCB trace for > equivalent length in SDRAM > data bus. I am very puzzled about it all the time I > think, for SDRAM > data bus, there is on need for equivalent trace > length in SDRAM data > bus. The timing is determined by the longest data > bus. For other SDRAM > data bus, the short, the better, and no need for > equivalent. Do you > think so? > > Also where can I find some detailed guide for SDRAM > and DDR tracing? > > Thanks in advanced > > Peter > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in > the Subject field > > or to administer your membership from a web page, go > to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the > Subject field > > List FAQ wiki page is located at: > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ > > List technical documents are available at: > http://www.si-list.org > > List archives are viewable at: =20 > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are > viewable at: > http://www.qsl.net/wb6tpu > =20 > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in > the Subject field > > or to administer your membership from a web page, go > to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the > Subject field > > List FAQ wiki page is located at: > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ > > List technical documents are available at: > http://www.si-list.org > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are > viewable at: > http://www.qsl.net/wb6tpu > > > __________________________________ Do you Yahoo!? The all-new My Yahoo! - Get yours free! http://my.yahoo.com ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu