[SI-LIST] Re: SDRAM timing
- From: "peter zhu" <peter.zhu@xxxxxxxxxx>
- To: <crjohnson11@xxxxxxxxxxx>
- Date: Tue, 30 Nov 2004 20:30:17 +0800
Johnson:
Thanks for your explaination.. In your mail, maintaining the equal lenth in
data bus is for a optimum point.
But you know, for some SDR SDRAM controller, the clock is from SDRAM
controller, we can not adjunt the clock forward. In fact, majority of SDR
SDRAM clock scheme is as such.
In such situation, I think the timing is only determined by the longest data
trace, and the shorter the better. Do you aggree with me?
Thinking about another clocking scheme in SDR SDRAM. The SDRAM controller
and SDRAM is clocked by the same external clock with same phase. In this
situation, I also think the timing is only determined by the longest trace,
and the shorter the better.
Regards
Peter
----- Original Message -----
From: "Christopher R. Johnson" <crjohnson11@xxxxxxxxxxx>
To: <peter.zhu@xxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Monday, November 29, 2004 11:20 PM
Subject: [SI-LIST] Re: SDRAM timing
> If you have zero skew (all lines the same length), then there is some
> optimum point at which you can place your clock to give the best setup and
> hold for all signals. Once you introduce skew between any of the signals,
> from trace length, different output prop delays, different receiver
> thresholds, clock jitter, etc. you no longer have a single point in the
> cycle which is best for all signals. Your best point is now fuzzed out to
a
> band of different best points across all of the signals. The best you can
> do is minimize the difference between the individual best clock placements
> and the actual clock placement. To do this, you place your clock midway
> between the best placement for slowest and fastest signals. The point at
> which the "fuzzed out" clock placement equals the system clock is the
> fastest that you can go.
>
>
> ----- Original Message -----
> From: "peter zhu" <peter.zhu@xxxxxxxxxx>
> To: <bmgman@xxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Sent: Monday, November 29, 2004 7:26 AM
> Subject: [SI-LIST] Re: SDRAM timing
>
>
> > Mike and all:
> >
> > I think the setup and hold time is not a problem in shortest data bus.
> > Assume that the length of data bus is ZERO, because no any data bus
delay,
> > so the timing will be just the timing in SDRAM or SDRAM controller
> > datasheet!!! It's perfect!
> > So I think the shorter, the better.
> > Can anybody explain it? Do we really need to maintain the almost same
> length
> > in SDRAM data bus?
> >
> > Thanks in advanced.
> >
> > Peter
>
>
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