[SI-LIST] Re: SDRAM timing
- From: "peter zhu" <peter.zhu@xxxxxxxxxx>
- To: <brian.p.moran@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Nov 2004 20:35:53 +0800
Brian:
I searched the intel website, and only found some docs for intel chipset
SDRAM design, and the design is only based on DIMM. In embed system, many
design need to solder SDRAM chip to motherbaord directly. Where can I find
such design guideline for SDRAM(SDR and DDR)?
Thanks
Peter
----- Original Message -----
From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
To: <peter.zhu@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, November 30, 2004 2:50 AM
Subject: [SI-LIST] Re: SDRAM timing
> Peter,
>
> There are of course numerous timing paths on a DDR2 interface. The
> primary paths associated with the data bus are DQ to DQS setup and hold
> margins, and the DQS to CLK setup and hold margins. The DQ to DQS timing
> is often discussed in terms of DQ to DQS skew, and is measured within
> each byte lane independently. To maximize these margins it is necessary
> to match each of the DQ signals to there associated DQS strobe, on a
> byte lane by byte lane basis. (In some cases there may be a fixed offset
> specified between DQ and DQS in order to center the setup and hold
> margins.) The overall length of the byte lane has only a second order
> impact on these calculations. The length range over which each byte lane
> may be routed as a group is usually fairly wide.=20
>
>
> The amount of length range over which the byte lanes may vary is
> controlled by the DQS to CLK path, for the most part. Here you have to
> worry about traditional setup and hold with respect to the clock. In
> this case the longest DQS signal will generally control setup margin and
> the shortest DQS will control hold margin.
>
> If you look at Intel guidelines for example, there is a spec for DQ to
> DQS length matching within a byte lane, which is generally on the order
> of DQ length =3D (DQS Length - Offset) +/-20 mils. Then there is a
> guideline for DQS vs CLK length matching which may be on the order of
> CLK - 2.0" </=3D DQS </=3D CLK + 1.0". This is just an example and you =
> need
> to consult the guidelines provided by your controller vendor, but this
> is how the guidelines are generally structured.
>
>
> Brian P. Moran=20
> SIE Engineer=20
> Intel Corporation=20
> brian.p.moran@xxxxxxxxx=20
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of peter zhu
> Sent: Friday, November 26, 2004 3:04 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] SDRAM timing
>
> Hi, all:
>
> I oftem see designer reel the PCB trace for equivalent length in SDRAM
> data bus. I am very puzzled about it all the time I think, for SDRAM
> data bus, there is on need for equivalent trace length in SDRAM data
> bus. The timing is determined by the longest data bus. For other SDRAM
> data bus, the short, the better, and no need for equivalent. Do you
> think so?
>
> Also where can I find some detailed guide for SDRAM and DDR tracing?
>
> Thanks in advanced
>
> Peter
>
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