[SI-LIST] Re: SDRAM timing

Can you say "skew"?  Unequal wire length = skew.

Regards

Mike


peter zhu wrote:

> Mike:
> 
> I think the setup and hold time is not a problem in shortest data bus. Assume 
> that the length of data bus is ZERO, so no any data bus delay,  the timing 
> will be just the timing in SDRAM or SDRAM controller datasheet!!! It's 
> perfect!
> So I think the shorter, the better.
> Can anybody explain it? 
> 
> Thanks in advanced.
> 
> Peter
> 
> 
> ----- Original Message ----- 
> From: "Mike Brown" <bmgman@xxxxxxxxxx>
> To: <peter.zhu@xxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Sent: Saturday, November 27, 2004 12:49 PM
> Subject: [SI-LIST] Re: SDRAM timing
> 
> 
> 
>>Peter,
>>You are half right.  Long path (setup) timing is determined by the longest 
>>data bus.  You fail to consider the short path (hold) timing, and you will 
>>get a really nasty surprise some time after the design is released to the 
>>customer by doing so.
>>
>>Mike
>>
>>peter zhu wrote:
>>
>>
>>>Hi, all:
>>>
>>>I  oftem see designer reel the PCB trace for equivalent length in SDRAM data
>>>bus. I am very puzzled about it all the time  I think, for SDRAM data bus,
>>>there is on need for equivalent trace length in SDRAM data bus. The timing
>>>is determined by the longest data bus. For other SDRAM data bus, the short,
>>>the better, and no need for equivalent. Do you think so?
>>>
>>>Also where can I find some detailed guide for SDRAM and DDR tracing?
>>>
>>>Thanks in advanced
>>>
>>>Peter
>>>
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>>
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