Posts for si-list, 12-2004

Browse: Last Month: 11-2004 Main Archive Page Next Month: 01-2005

» [SI-LIST] Wishing All A Happy n Prosperous New Year 2004 -
» [SI-LIST] Job Opportunity -
» [SI-LIST] Re: Windows-based schematic editors -
» [SI-LIST] Sources for Electronics Books, Standards, and Equipment Manuals -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Big Hspice Netlist Question -
» [SI-LIST] si-list online FAQ vandalism repaired -
» [SI-LIST] Re: Simulation Problem -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Simulation Problem -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Package design considerations -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Series termination: common mode -
» [SI-LIST] Series termination: common mode -
» [SI-LIST] Re: Big Hspice Netlist Question -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Big Hspice Netlist Question -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: PLL Jitter measurement -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: What are eye patterns -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] PLL Jitter measurement -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: ICM model support in Hspice -
» [SI-LIST] ICM model support in Hspice -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: What are eye patterns -
» [SI-LIST] Re: What are eye patterns -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Series termination -
» [SI-LIST] What are eye patterns -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Series termination -
» [SI-LIST] Coupled Lines Modeling -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] ATX Power Supply Question -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Anand Haridass is out of the office until 01/03/2005 -
» [SI-LIST] Senior Level EMC/SI Consultant -
» [SI-LIST] Re: Inductance of PWR&GND plane and other signal line -
» [SI-LIST] Re: Inductance of PWR&GND plane and other signal line -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] Re: Tip & Ring Signals -Reg -
» [SI-LIST] Re: Semi Website -
» [SI-LIST] Re: Tip & Ring Signals -Reg -
» [SI-LIST] Re: Inductance of PWR&GND plane and other signal line -
» [SI-LIST] Re: Rocket I/O pcb layout -
» [SI-LIST] Re: Rocket I/O pcb layout -
» [SI-LIST] Rocket I/O pcb layout -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] What is FailSafe/Non-Failsafe ESD. -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Inductance of PWR&GND plane and other signal line -
» [SI-LIST] Re: Tip & Ring Signals -Reg -
» [SI-LIST] Tip & Ring Signals -Reg -
» [SI-LIST] Inductance of PWR&GND plane and other signal line -
» [SI-LIST] PIPE specification for PCI Express -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: material to be sued at 200-500degC -
» [SI-LIST] Re: raguraman(doubt on clk buffer) -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Adjacent Power Plane Noise Coupling -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] 802.3ap -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: material to be sued at 200-500degC -
» [SI-LIST] material to be sued at 200-500degC -
» [SI-LIST] Re: SI Positions / Device charaterization and Modelling Positions -
» [SI-LIST] Re: SI Positions / Device charaterization and Modelling Positions -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Article discussion on bad packages -
» [SI-LIST] Re: thermal via in BGA's -
» [SI-LIST] Re: raguraman(doubt on clk buffer) -
» [SI-LIST] raguraman(doubt on clk buffer) -
» [SI-LIST] Adjacent Power Plane Noise Coupling -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Intel Signal Integrity Opportunities -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] thermal via in BGA's -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Question about transistors. -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Question about transistors. -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] European IBIS Summit At DATe 2005 -First Call for Paper/Call for Participation -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Test -
» [SI-LIST] Re: Question about transistors. -
» [SI-LIST] Question about transistors. -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Test, are we active? -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Re: Chassis and Signal ground -
» [SI-LIST] Chassis and Signal ground -
» [SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Strange Gnd Clamp V-I curve when generating IBIS -
» [SI-LIST] Re: From a 1954 Issue of Popular Mechanics... -
» [SI-LIST] From a 1954 Issue of Popular Mechanics... -
» [SI-LIST] ATC Buss Spec's -
» [SI-LIST] Re: clamping doide function in receiverside -
» [SI-LIST] clamping doide function in receiverside -
» [SI-LIST] Re: FW: radial cracks around thru-holes in Polyimide laminate - root cause -
» [SI-LIST] Re: Intel looking for SI engineer -
» [SI-LIST] Intel looking for SI engineer -
» [SI-LIST] PCB Designer available -
» [SI-LIST] Re: S-Parameter and Harmonics Balance Analysis -
» [SI-LIST] Re: DDR compatibility issue -
» [SI-LIST] Re: EBD file for BGA resistor network -
» [SI-LIST] Re: EBD file for BGA resistor network -
» [SI-LIST] EBD file for BGA resistor network -
» [SI-LIST] S-Parameter and Harmonics Balance Analysis -
» [SI-LIST] Course in Digital Systems Engineering offered through Stanford University -
» [SI-LIST] Re: DDR compatibility issue -
» [SI-LIST] Re: DDR compatibility issue -
» [SI-LIST] Re: DDR compatibility issue -
» [SI-LIST] Re: DDR compatibility issue -
» [SI-LIST] DDR compatibility issue -
» [SI-LIST] Verifying the IBIS model of ICS8432-51 -
» [SI-LIST] Locating impusle and ESD events -
» [SI-LIST] Re: Mictor connector model -
» [SI-LIST] Re: Mictor connector model -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Any spice benchmarks? -
» [SI-LIST] Re: Mictor connector model -
» [SI-LIST] Re: Any spice benchmarks? -
» [SI-LIST] Re: Looking for SI engineer -
» [SI-LIST] Re: Mictor connector model -
» [SI-LIST] Any spice benchmarks? -
» [SI-LIST] Mictor connector model -
» [SI-LIST] Re: Looking for SI engineer -
» [SI-LIST] Re: Looking for SI engineer -
» [SI-LIST] Looking for SI engineer -
» [SI-LIST] Re: getting info from freelist/archive -
» [SI-LIST] getting info from freelist/archive -
» [SI-LIST] Re: DC DC converter routing -
» [SI-LIST] DC DC converter routing -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: pll's closed-loop using mathcad -
» [SI-LIST] pll's closed-loop using mathcad -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: FW: radial cracks around thru-holes in Polyimide laminate - root cause -
» [SI-LIST] Re: High Voltage Stackup -
» [SI-LIST] Re: Return Current distribution in 3-2-3 build-up Substrate stackup -
» [SI-LIST] Re: High Voltage Stackup -
» [SI-LIST] Re: Return Current distribution in 3-2-3 build-up Substrate stackup -
» [SI-LIST] Re: Ragu-help -
» [SI-LIST] High Voltage Stackup -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Return Current distribution in 3-2-3 build-up Substrate stackup -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] FW: radial cracks around thru-holes in Polyimide laminate - root cause -
» [SI-LIST] Return Current distribution in 3-2-3 build-up Substrate stackup -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Ragu-help -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Split power plane and long return current path -
» [SI-LIST] FW: radial cracks around thru-holes in Polyimide laminate - root cause -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: Power distibution network modeling -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] impedance change -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: SI Tutorials on DVD -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Power distibution network modeling -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] SI Tutorials on DVD -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: stripline return paths etc. -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] stripline return paths etc. -
» [SI-LIST] DC and AC specification -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Tool feedback -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: PCI and Spread Spectrum Clocking -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Why is capacitor with high ESR -
» [SI-LIST] Re: Dielectric loss modeling -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Power supply isolation. -
» [SI-LIST] Re: Dielectric loss modeling -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] Re: Example microstrip file for FlexPDE ??? -
» [SI-LIST] Re: Ragu help on board -
» [SI-LIST] Re: EMI simulation tools at PCB level -
» [SI-LIST] EMI simulation tools at PCB level -
» [SI-LIST] unsubscribe -
» [SI-LIST] Why is capacitor with high ESR -
» [SI-LIST] Example microstrip file for FlexPDE ??? -
» [SI-LIST] Re: SDRAM Blowup! -
» [SI-LIST] Outsourcing -
» [SI-LIST] Re: IBIS basic question -
» [SI-LIST] Re: SDRAM Blowup! -
» [SI-LIST] Re: IBIS basic question -
» [SI-LIST] Re: (no subject) -
» (no subject) -
» [SI-LIST] Re: Ragu help on board -
» [SI-LIST] Re: UL standard -
» [SI-LIST] UL standard -
» [SI-LIST] Re: About Tco -
» [SI-LIST] Ragu help on board -
» [SI-LIST] IBIS basic question -
» [SI-LIST] Re: Embedded Engineer position in Southern CA -
» [SI-LIST] Re: Power and Ground Plane area -
» [SI-LIST] Embedded Engineer position in Southern CA -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: multiple pairs of waveform in IBIS -
» [SI-LIST] Re: Capacitor with high ESR -
» [SI-LIST] Re: Power and Ground Plane area -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: Power and Ground Plane area -
» [SI-LIST] Re: Capacitor with high ESR -
» [SI-LIST] Re: multiple pairs of waveform in IBIS -
» [SI-LIST] Re: Capacitor with high ESR -
» [SI-LIST] Re: Capacitor with high ESR -
» [SI-LIST] Re: Power and Ground Plane area -
» [SI-LIST] Power and Ground Plane area -
» [SI-LIST] Hspice models from S param analysis -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: PCB Layer Stack up -
» [SI-LIST] Re: SUPERCAP -
» [SI-LIST] SUPERCAP -
» [SI-LIST] Re: Dielectric loss modeling -
» [SI-LIST] Capacitor with high ESR -
» [SI-LIST] Re: PCB Layer Stack up -
» [SI-LIST] Re: Dielectric loss modeling -
» [SI-LIST] multiple pairs of waveform in IBIS -