[SI-LIST] Re: Can EMI be reduced by offset clocks
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Nov 2004 10:34:07 -0500
> We are encounter some EMI problem on 6x PCI 33 MHz clocks. If I
> stagger these six clocks by 0.2 ns seconds away (assume the time
> margin still meets) will it help EMI ?
I think in principle it might, but maybe not.
In the time domain the offset would need to be significant with respect to
the clock signal's risetime. By doing so, the edges would be skewed from
one another and wouldn't all coincide, which would reduce the peak current
in the return path too.
In the frequency domain, you should consider what frequencies are failing.
This 0.2 ns corresponds to some phase shift at each harmonic frequency, and
at high enough harmonics (in the vicinity of the 75th harmonic), the phase
shift could give you some cancellation and EMI reduction. To get reduction
of the 7th harmonic, the skew would need to be 2.1 ns.
But part of the trick would be to make the skew predictable, to keep it
consistent. What if one clock fanout part happened to have its outputs
skewed 0.2 ns in the opposite direction? Plus, variations in loading on the
clock pin from different PCI cards, would affect the results too.
Regards,
Andy
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