[SI-LIST] PCB stack issue

  • From: "sunil Morajkar" <msunil@xxxxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 13 Nov 2004 19:14:44 +0530

hello all,

         I am doing a 8 layer mixed signal layer PCB in which analog
cicuitary & voltages are scattered on the board making four different
area.Rest every where digital signals are running. I have 8 layers stack as
follows

        1. top (ananlog + digital signals)
        2. gnd( ananlog plane)
        3. inner1 (digital signals only)
        4. gnd ( ananlog plane)
        5. power( analog plane)
        6. inner2 (digital signals only)
        7. power (digital plane)
        8. bot (digital & analog signals)

i have a fear of having analog planes as it will simply come below some of
the digital circuitary, which will create problems

I would like to have opinion/advice whehter to continue with same stack or
to have split planes. I mean should i have all digital ground & digital
power on which i will create analog island for power & ground.

waiting for reply

regds
sunilm




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Neven Orhanovic
Sent: Saturday, November 13, 2004 11:49 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Question on 2D field solver


Dear Ray and all SI folks:

The question about the self inductance of a pair of long cylindrical
parallel wires in free space deserves another reply.

As Raj already pointed out, the total inductance L(f) consists of
two parts, the external inductance and the internal inductance.
Most simple RLGC solvers give only the external inductance which
can be considered as frequency independent. For this problem,
the exact external inductance (per unit length) is

  L_external = L(f=infinity) =
             = mu_0/pi * arcosh(d/(2*a))
             = 4e-7 * arcosh(500/150) = 749.53... nH/m,

where d is the center-to-center distance between the wires and
a is the wire radius.

The approximate external inductance, neglecting the proximity
effect (assuming that the wire current is circumferential about
the wire axis), is

  L_external_approx = mu_0/pi * ln(d/a) =
                    = 4e-7 * ln(500/75) = 758.85... nH/m.

I think that this is the difference that Ray is seeing.

For this problem, the relative difference between the L_external
result that neglects the proximity effect and the one that
includes it is only about 1%. If the conductors are brought closer
together, this difference will be larger.

The second part of the inductance L(f) is the internal inductance
L_internal(f). The approximate internal inductance at f=0 for this
problem (neglecting the proximity effect) is

  L_internal_approx(f=0) = mu_0/(4*pi) = 100 nH/m

giving a total DC inductance of

  L(f=0) = 100 nH/m + 749.53 nH/m = 849.53 nH/m.

Between f=0 and f=infinity, the inductance will drop from a value
of approximately 849.53 nH/m to 749.53 nH/m.

Should one worry about 1% differences in the computed inductance
at f=infinity while neglecting the (much larger) frequency variation
of the inductance at lower frequencies?
I think, no.

Finally, here are a few R(f),L(f) values for one half of this problem
computed using the Finite Element Method (ApsimRLGC, method=3):

       f [Hz]     R [ohm/m]      L [H/m]
           0       0.976304     4.27384e-07
       1e+06        1.01551     4.26106e-07
       1e+07         2.1033     4.01947e-07
       1e+08        6.09936     3.84594e-07
       1e+09        18.9998     3.76962e-07
       1e+10        59.8103     3.75390e-07

For the full problem, the values need to be multiplied by 2.
Copper was assumed for the wires with mu_r=1 and sigma=5.8e7 S/m.

Best regards,
Neven Orhanovic
Applied Simulation Technology
www.apsimtech.com

On Wed, 2004-11-10 at 23:24, Raymond Anderson wrote:
> Here's a question for the field solver guru's on the list:
>
> I'm currently taking a critical look at the Mayo  MMTL BEM  2D field
> solver (TNT 1.2.2) that the developers at Mayo have so graciously made
> freely available under the GNU GPL to the  world. See the si-list
> message announcing it for download links:
> (//www.freelists.org/archives/si-list/07-2004/msg00311.html)
>
> In preparation for doing a series of simulations on some via geometries
> in packages I decided to validate the accuracy of the MMTL program on
> some simple geometries that independent high accuracy answers were known
> for.
>
> I first tried the zero thickness stripline benchmark suggested by Dr.
> Rautio at Sonnet Software.
> (http://www.sonnetusa.com/products/benchmarking/eval_ch3.asp). The
> results were   about   -0.4% low at 49.8002 ohms.  This compares
> comparably with a selection of other solvers I've had access to  (but on
> the low end of the range).
>
> Mayo MTTL                         49.8002
> Polar CITS25                        49.96
> Agilent Appcad 3.0.2             49.8
> AWR TXLINE                      50.0346
> LINPAR 2.0                          50.03
> LINPAR 1.0                          50.027
>
> Next I selected the case of a pair of parallel round elements  as a test
> case. The analytical solution for the inductance of this geometry is
> given by Grover in chapter 5 of "Inductance Calculations". His formula
> is an analytic solution based on first principles.
>
> Using a test case  of  conductors 150 microns in diameter on a 500
> micron pitch, Grover's equations yields  a loop inductance of
> 758.84797  nH for 1 meter long conductors. The same problem modeled in
> the MMTL field solver gives  an answer of  749.4645  nH.  I'm  trying to
> understand why the field solver answer is about 1.2% low. Is this
> reasonable for a 2D MOM BEM solver using quasi-TEM assumptions? I've
> tried modeling it several ways (as  a pair of parallel circular
> conductors far from ground and as a single circular conductor with it's
> image reflected across a ground plane) and  am getting the same answer
> out to at least 2 decimal places. I've also tried upping the density of
> the meshing  with little real improvement.
>
> Comments, suggestions and ideas solicited. Thanks!
>
> -Ray Anderson
>
> Senior Signal Integrity Staff Engineer
> Advanced Packaging R&D
> Xilinx Inc.
>
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