Posts for si-list, 05-2005

Browse: Last Month: 04-2005 Main Archive Page Next Month: 06-2005

» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: N-port s-parameter -
» [SI-LIST] N-port s-parameter -
» [SI-LIST] Re: Decoupling Using 3-Terminal Capacitor -
» [SI-LIST] Re: Decoupling Using 3-Terminal Capacitor -
» [SI-LIST] Re: Decoupling Using 3-Terminal Capacitor -
» [SI-LIST] Re: Decoupling Using 3-Terminal Capacitor -
» [SI-LIST] Decoupling Using 3-Terminal Capacitor -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: Scale option in Hspice -
» [SI-LIST] Re: Scale option in Hspice -
» [SI-LIST] Re: ISI Jitter -
» [SI-LIST] ISI Jitter -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Simulation of Frequebcy Selective (FSS) and Periodic (PS) Structures in HFSS -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: ETX -module EBD model -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] Re: High speed signal on top layer -
» [SI-LIST] ETX -module EBD model -
» [SI-LIST] RF design guidelines?? -
» [SI-LIST] High speed signal on top layer -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: Scale option in Hspice -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: SPICE inaccuracies (was Re: SI models at MGH speeds) -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: SPICE inaccuracies (was Re: SI models at MGH speeds) -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Scale option in Hspice -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] DDR2 on-die termination 75ohm and 50ohm -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] Re: FW: SI models at MGH speeds -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: Determination of relative permittivity -
» [SI-LIST] S11 or S21 -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] Re: Calculating the Z0 of a trace -
» [SI-LIST] Unsubscribe -
» [SI-LIST] Re: SI models at MGH speeds -
» [SI-LIST] Re: Determination of relative permittivity -
» [SI-LIST] Re: Determination of relative permittivity -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Calculating the Z0 of a trace -
» [SI-LIST] Re: Calculating the Z0 of a trace -
» [SI-LIST] Calculating the Z0 of a trace -
» [SI-LIST] Re: Determination of relative permittivity -
» [SI-LIST] SI models at MGH speeds -
» [SI-LIST] Re: Determination of relative permittivity -
» [SI-LIST] Determination of relative permittivity -
» [SI-LIST] Re: starter -
» [SI-LIST] Re: starter -
» [SI-LIST] R: starter -
» [SI-LIST] starter -
» [SI-LIST] Re: Wide input range LDO -
» [SI-LIST] power spectral density -
» [SI-LIST] Re: Wide input range LDO -
» [SI-LIST] Re: Wide input range LDO -
» [SI-LIST] Wide input range LDO -
» [SI-LIST] Wide input range LDO -
» [SI-LIST] Wide input range LDO -
» [SI-LIST] Re: Embedded Resistors -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Definition of spreading inductance -
» [SI-LIST] Re: Definition of spreading inductance -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Definition of spreading inductance -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Embedded Resistors -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] Re: some question about JFET or MOSFET -
» [SI-LIST] some question about JFET or MOSFET -
» [SI-LIST] Re: 10-Layer Stack up -
» [SI-LIST] 10-Layer Stack up -
» [SI-LIST] Hi-pot test requirement for router. -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Do i have to use microstrip lines? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: How to simulate 2 components each having its own process file in Hspice -
» [SI-LIST] SI career path -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] How to simulate 2 components each having its own process file in Hspice -
» [SI-LIST] How to simulate 2 components each having its own process file in Hspice -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Modal Currents and Voltages -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Estimate ISI with S parameters -- Using TDR to do SDD21 correlation? -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] IBIS Summit Second Call for Papers - DAC June14th, 2005, Anaheim CA -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Capacitivly Coupled Interfaces -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: si-list Digest V5 #210 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] 2006 EMC Symposium in Singapore -
» [SI-LIST] Re: Capacitivly Coupled Interfaces -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Capacitivly Coupled Interfaces -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Capacitivly Coupled Interfaces -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Re: How to Measure Ground Noise -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Estimate ISI with S parameters? -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Re: Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Routing 10G differential lines over Standard FR-4 -
» [SI-LIST] Decoupling capacitors -
» [SI-LIST] Re: Low Temperature Limit -
» [SI-LIST] Re: Low Temperature Limit -
» [SI-LIST] Low Temperature Limit -
» [SI-LIST] Re: Estimate ISI with S parameters? -
» [SI-LIST] Re: Estimate ISI with S parameters? -
» [SI-LIST] Re: Do i have to use microstrip lines? -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] Re: Do i have to use microstrip lines? -
» [SI-LIST] Do i have to use microstrip lines? -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] Re: difference between two batches of main boards? -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: Voids in BGA joints -
» [SI-LIST] Re: hfss 9.2 -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: hfss 9.2 -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Re: Estimate ISI with S parameters? -
» [SI-LIST] Re: Estimate ISI with S parameters? -
» [SI-LIST] Voids in BGA joints -
» [SI-LIST] Re: 20%-80% rise time -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] Re: 20%-80% rise time -
» [SI-LIST] Re: 20%-80% rise time -
» [SI-LIST] Re: The function of VBW in spectrum analyzer -
» [SI-LIST] 20%-80% rise time -
» [SI-LIST] The function of VBW in spectrum analyzer -
» [SI-LIST] reg VOIP -
» [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] How can I simulate the influence of power plane noise on the signal trace ? -
» [SI-LIST] Estimate ISI with S parameters? -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] hfss 9.2 -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Re: Discontinuities on PCB -
» [SI-LIST] Discontinuities on PCB -
» [SI-LIST] SI position in Sunnyvale, CA -
» [SI-LIST] Re: ground conductors on TNT -
» [SI-LIST] Re: ground conductors on TNT -
» [SI-LIST] Re: ground conductors on TNT -
» [SI-LIST] Re: ground conductors on TNT -
» [SI-LIST] ground conductors on TNT -
» [SI-LIST] Apple Needs Good SI People -
» [SI-LIST] IEEE-EMCS SCV Chapter meeting on Tuesday May 10, 2005 -
» [SI-LIST] RMCEMC Presentation download available -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: DDR2 unbuffered DIMM specification? -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] DDR2 unbuffered DIMM specification? -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e-xx ?" -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?" -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] Re: PI Analysis about Core Power Supply -
» [SI-LIST] PI Analysis about Core Power Supply -
» [SI-LIST] Re: Metal Fills? -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Metal Fills? -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Probe headers on DDR SDRAM -
» [SI-LIST] JEDEC 1.8V HSTL Interface -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Experimental/Prototype Supplies -
» [SI-LIST] Probe headers on DDR SDRAM -
» [SI-LIST] Re: Maximum length of 1000basetT diff pair traces from PHYs to magnet ics -
» [SI-LIST] Re: Curved vs. 90 degree PCB trace paper -
» [SI-LIST] Comments on "Do you really ship products at BER 10e-xx ?" -
» [SI-LIST] Re: RC time constant question -
» [SI-LIST] Re: Maximum length of 1000basetT diff pair traces from PHYs to magnet ics -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Curved vs. 90 degree PCB trace paper -
» [SI-LIST] Re: Curved vs. 90 degree PCB trace paper -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Curved vs. 90 degree PCB trace paper -
» [SI-LIST] Curved vs. 90 degree PCB trace paper -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Maximum length of 1000basetT diff pair traces from PHYs to magnet ics -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Re: Broadside coupled line vertical registration -
» [SI-LIST] Broadside coupled line vertical registration -
» [SI-LIST] Passivity of an Inductance Matrix -
» [SI-LIST] Re: RC time constant question -
» [SI-LIST] RC time constant question -
» [SI-LIST] Re: doubt in pci interface -
» [SI-LIST] doubt in pci interface -
» [SI-LIST] [Fwd: [IBIS-Users] IBIS Summit First Call of Papers - DAC June14th, 2005, Anaheim CA] -
» [SI-LIST] verification of current measurements -
» [SI-LIST] Out of Office AutoReply: -
» [SI-LIST] Re: power plane question -
» [SI-LIST] power plane question -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] IBIS Models -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: 1000BASE-SX -
» [SI-LIST] 1000BASE-SX -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace - Ansoft/P olar -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: Need advice on basic 6-layer stackup -
» [SI-LIST] Re: Finding the impedance of a PCB trace -
» [SI-LIST] Re: chapter 1 of Signal Integrity Simplified as pdf on web site -
» [SI-LIST] Re: chapter 1 of Signal Integrity Simplified as pdf on web site -
» [SI-LIST] Re: chapter 1 of Signal Integrity Simplified as pdf on web site -
» [SI-LIST] Question about Academics -
» [SI-LIST] chapter 1 of Signal Integrity Simplified as pdf on web site -
» [SI-LIST] Re: volume resistivity (or conductivity) of printed circuit boards -
» [SI-LIST] Re: volume resistivity (or conductivity) of printed circuit boards -
» [SI-LIST] volume resistivity (or conductivity) of printed circuit boards -