[SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- Date: Sat, 14 May 2005 22:14:31 -0700
Jeff, your assumption is not part of Zhangkun's statement, nor any of my
comments. Were a pair strongly referenced to common, and only weakly
coupled to some other source the likelihood of excessive noise is USUALLY
low. An exception might occur when dealing with special cases where signal
amplitude ratios are very high. Think things like line cards, ignition
controllers and other devices that live outside a digital chip to digital
chip universe despite things like isolation transformers with limited
CMRR. Or for a situation that is likely more near and dear, think about
what happens going through connector pin fields, or even Z axis escape
inside packages with inadequate return chevrons.
ADI's current "Designer's Guide to Instrumentation Amplifiers" does a nice
treatment on RF rectification ( ie exceeding the CM voltage range ) in
amplifier front-ends and the effects in instrumentation land. The
phenomenon is the same with high bandwidth digital signaling. Bandwidth
does not change the CM range of an emitter, or source coupled pair. The
problem is particularly severe as the signal level goes towards the source
/ emitter current feed supply rail. If the current feed is done with a
simple resistor, then theoretically we can reach down almost to
Vbe/Vgs. If the feed is done with a current sink/source, then we are
further limited. In Op-Amp land they have played some tricks to extend the
CM voltage range by using matched pairs of transistors that are
complementary types to the diff pair itself. Usually, a big price for this
is speed. The original poster child for this technique was the ancient
LM324 that as I recall used matched PNP darlingtons on each side of the
input diff pair. LTI has some interesting parts they dub "Beyond the Rail"
that use similar techniques in CMOS. Maybe an LSI I/O designer would care
to comment if any similar techniques are in current use for high speed
differential front-ends.
If you want to argue that by strongly referencing the common reference for
the receiver one can restrict the noise, I agree. How much matters seems
to be the question, which goes right back to my comment about "it is all
about the coefficients". If there is little noise injection in the Vcc
plane, or the Vcc / Common cavity is very low impedance and cavity
resonance is not an issue, then the coefficients would be small. Look back
at all the discussions of various band-aid methods of fixing poor board
designs including application of lots of otherwise unnecessarily thin and
expensive dielectric to get the signaling in-line. If we reference some
arbitrary voltage plane without doing requisite homework, we are asking for
trouble. I don't know how many times Chris Cheng has tried to drive this
message home when discussing return paths.
If you want to characterize, you need to understand: the noise current
sources, and the return path including, where applicable, cavity
effects. One way to avoid that analysis is not to go down that road which
is the simplest and if economically available, my first choice. It is the
designer's choice and responsibility to choose and act accordingly.
So let's take your experiment. Go ahead and use a TDR and then start
really cranking up the RF generator signal. Eventually you will overwhelm
the TDR receiver front end. At what level depends on the specs for the
TDR. It might take an ESD discharge magnitude signal to finally overwhelm
the CM voltage range ( assuming some sort of isolation transformer in the
TDR ), but you can certainly get there eventually. Assuming warranty is
not an issue, it could be an enlightening experiment.
But I have a different experiment that I think would be a more salient
demonstration:
Build a stack-up:
Signal Microstrip edge coupled diff pair from source to receiver
Plane 1 Floating Drive w/ RF generator through a wide bandwidth 10:1
transformer located very close to the receiver.
Plane 2 Power supply common
Signal ( just for balance )
For added fun, set the plane dimensions so that the first half wave cavity
resonance lines-up with either the clock rise time frequency component, or
for added fun the clock frequency. Drive a diff clock pair routed on
Signal from source to receiver from an on-board low jitter crystal
oscillator. Measure the receiver output jitter as you increase the voltage
drive on the RF generator. My contention is that you will see a relatively
smooth and limited degradation in jitter until a point at which it sharply
inflects upward. That will be where you have hit the common mode voltage
limits of your receiver.
Regards,
Steve.
At 02:20 PM 5/14/2005 -0700, Loyer, Jeff wrote:
>Hi Steve,
>I'm also a bit curious about your comment, and wonder if others agree.
>Do you have any papers I could refer to that clearly document this
>occurring? Maybe I'm missing something, but assuming the traces are
>closer to the ground plane than the power plane (or at least no further
>than), it seems like if:
>1) the planes are very close together, the inter-plane capacitance would
>keep the AC potential between the planes at 0, or
>2) the planes are far apart, there wouldn't be substantial noise coupled
>from the power plane to the traces.
>
>Hmmm - I wonder what would happen if I went in the lab and, for the
>stackup described, hooked up a signal generator between the power and
>ground planes. What would I see on a TDR (which is referenced to
>ground)? I don't think I'd see effects from the induced noise. Perhaps
>if I injected the signal using ground as a reference and then used the
>power plane as the reference plane at the receiver - bad. The amplitude
>of the signal would vary with the noise.
>
>But I'd sure like to see where this effect is quantified (which is what
>I think the original intent was). Besides a rule-of-thumb that says
>"don't ever do it!", how can we characterize it and decide when it's ok
>and not?
>
>For Zhangkun - I'd be leery of referencing high-speed signals to power.
>As has been pointed out on this list before, at some point you probably
>have to get back to ground reference, and that can be problematic.
>
>
>Jeff Loyer
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of zhangkun 29902
>Sent: Friday, May 13, 2005 5:22 PM
>To: weirsi@xxxxxxxxxx
>Cc: jgxian@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: How can I simulate the influence of power plane
>noise on the signal trace ?
>
>Steve
>
>In the realistic, there have to be some signal refered to power plane.
>Moreover, I do not think it is very cirtical if the decoupling for the
>power delivery system.
>
>I have use 3D field solver to simulate this kind of situation. There is
>displacement current between planes, which gives rise to problem. If the
>displacement current could be lessen, I think it is no critical for the
>signal to refer to any plane.
>
>Best Regards
>
>Zhangkun
>2005.5.14
>
>----- Original Message -----
>From: steve weir <weirsi@xxxxxxxxxx>
>Date: Saturday, May 14, 2005 1:43 am
>Subject: [SI-LIST] Re: How can I simulate the influence of power plane
>noise on the signal trace ?
>
> > Jia, if you assume that:
> >
> > 1. The geometry of each line is identical
> > 2. The noise does not violate the CM range of the receiver,
> > 3. The CM rejection of the receiver is perfect
> >
> > Then you will not see any effects whatsoever. Put in more
> > realistic models
> > for each point above and you will find:
> >
> > 1. Differential noise injection
> > 2. Very bad if this happens, don't let it!
> > 3. Increased jitter
> >
> > For these reasons, it is a poor idea to reference high performance
> > links
> > against multiple voltage rails. It doesn't mean that you cannot
> > do it
> > successfully, but it does mean that you have a lot of additional
> > homework
> > to do, and may not be able to meet a given performance target.
> >
> > Steve.
> > 11:47 AM 5/13/2005 +0800, Jia Gongxian wrote:
> > >Dear all,
> > >
> > >I'd like to simulate the influence of power plane noise on the
> > signal
> > >traces, which are differential stripline, using the power plane
> > as one
> > >reference plane.That is,
> > >
> > > ----------------------------------- ground plane
> > >
> > > --- --- differential traces
> > >
> > > ----------------------------------- power plane + noise
> > >
> > > Any suggestions will be welcome.
> > >
> > >Thanks.
> > >
> > >Jia Gongxian
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