[SI-LIST] Re: starter

I don't know if this answers your question ... but traditional TTL outputs
have a MUCH stronger pull-down than pull-up driver.  Thus, it would not
surprise me to see ringing on the falling edge only.

Also the normal bipolar TTL output driver is unable to drive all the way to
Vdd (or Vcc) without help.  The pull-up transistor runs out of steam well
before then, and the shape of its I-V curve is very different from that of
the pull-down transistor.  It doesn't extrapolate towards Vcc.

Adding a 1K pull-DOWN resistor makes this unbalance even worse.  My
recollection is that a pull-down resistor in the few 100s of ohms would make
TTL marginal in the high state.

I don't know what you mean by balanced drive.  Is this the TTL 7474
flip-flop, or something else?  It shouldn't have balanced drive.  TTL wasn't
designed that way.

TTL inputs have clamp diodes that conduct when the input goes below ground,
part of whose purpose is to restrict the down-going overshoot on those
falling edges.  Sometimes this is called "diode termination."

Regards,
Andy



> I downloaded Pspice student and tried to model transmission line ringing.
> A 7474 (pspice) driving a non-lossy transmission line. No termination.
> output of the transmission line is connected to another 7474 input. I also
> have a 1K connected to GND at the o/p of transmission line. The
> transmission line shiled is connected to GND at both ends.
>
> When I simulate, I see ringing only on falling edge! Why is there no
> ringing on rising edge? The rising edge comes out as a capacitive rise
> time.
>
> I tried removing the 7474 at the o/p of the transmission line - i.e.-only
> 1K resisitor at the o/p. This behaves same.
>
> The digital IO model seems balanced on drive circuit. approx. 100OHM in
> both low and high.


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