[SI-LIST] Re: S11 or S21
- From: steve weir <weirsi@xxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx, "Larry Smith" <larry.smith@xxxxxxx>, adsurevv@xxxxxxxxx
- Date: Sat, 28 May 2005 15:51:38 -0700
Lee, the performance as shown by John's measurements, verifiable by theory,
and field solver results shows how dramatic component reduction can be
achieved with IDC capacitors, and X2Ys which both occupy the top of the low
inductance mountain. If you refer to my papers, I offer tabulations of
replacement ratios for various mounted configurations, including with vias
extending far beyond layers 2 or 3.
Cost versus value for the IDCs depends on what is more valuable, dollars,
or blocked routes and real estate. For X2Ys, it is a no brainer, because
they actually save money, quite a lot of it to be exact once placement and
drilling costs are accounted for. People who follow the advice of the
using the cheapest cost for the raw component lose money to their
competitors who know better.
Steve.
At 04:23 PM 5/27/2005 -0700, Lee Ritchey wrote:
>Steve,
>
>You haven't burst my baloon. I have paid attention to John Zasio's work in
>the book we cowrote. Figure 34.10 on page 138 shows four different sets of
>meaurements of capacitors mounted various ways, including IDCs. These
>measurements are taken with the capacitors hooked up to the first two
>planes below the surface of the PCB. Yes, the IDC is electrically better,
>but not enough so as to warrant their extra cost. Again, this similar
>performance is due to mounting inductance. When these capacitors are
>connected to planes lower in the PCB, the result is even worse.
>
>When X2Y capacitors are mounted in a similar way, the results are also
>similar. Yes, we have done those tests, too. Perhaps John would care to
>chime in here.
>
>
>
>Lee W. Ritchey
>Speeding Edge
>P. O. Box 2194
>Glen Ellen, CA 95442
>Phone- 707-568-3983
>FAX- 707-568-3504
>
>I just used the energy it took to be angry to write some blues.
>Count Basie
>
>
> > [Original Message]
> > From: steve weir <weirsi@xxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; Larry Smith <larry.smith@xxxxxxx>;
><adsurevv@xxxxxxxxx>
> > Cc: <si-list@xxxxxxxxxxxxx>
> > Date: 5/27/2005 3:56:39 PM
> > Subject: Re: [SI-LIST] Re: S11 or S21
> >
> > Lee, I hate to burst your balloon, but you would do well to pay attention
> > to the test data that John Zasio presents in your book "Right the First
> > Time" If I recall correctly his comparison of various mounted capacitor
> > performance including 0612 IDCs may be found in Chapter 36 ( might be 35
>or
> > 37 ). While it is true that vias, and particularly long vias diminish
>the
> > advantage of low inductance capacitors, on average IDCs and X2Ys make
>more
> > efficient use of vias than doubling up vias on conventional caps. This
>can
> > also be determined from John's data in your book. Doubling up vias on
> > conventional caps reduces conventional cap count but increases total vias
> > and blocked routes compared to simply using conventional caps, or
>properly
> > applying low inductance caps.
> >
> > While IDCs are quite expensive, other ultalow inductance capacitors, like
> > X2Ys are not. The performance advantages in terms of component count,
> > vias, and overall cost can be found in several of my presentations
> > available at the X2Y web site www.x2y.com, and the Teraspeed web site
> > www.teraspeed.com, including my DesignCon 2005 paper "High Performance
>FPGA
> > Bypass Networks".
> >
> > As to whether IDCs which do cost a lot, Teraspeed has customers who do
>not
> > have X2Y on their AVL, and for whom IDC provides superior value, because
> > space, and not raw component cost is the premium value.
> >
> > Steve
> > At 02:53 PM 5/27/2005 -0700, Lee Ritchey wrote:
> > >Virenda,
> > >
> > >To add to what Larry has said, if you are interested in the parasitic
> > >inductance of a capacitor as it relates to using the part as part of your
> > >power bypassing, it will turn out that the mounting inductance will
> > >dominate over the parts parasitic inductance. Part of this is due to the
> > >inductance of the vias needed to connect the capacitor to the power
>planes
> > >it is used with and part of it is due to the size of the mounting
>structure
> > >needed to solder the part to the PCB.
> > >
> > >Tests have shown that once you have to reach planes deeper into the PCB
> > >than 10 or so mils, the value of ultra low inductance parts such as IDC
>is
> > >masked to the point they are not worth the extra cost. (The inductand of
> > >vias is about 35 pH per mil of length. With two of these, reaching just
>20
> > >mils into the PCB results in almost .7 nH just from mounting vias.
>Doesn't
> > >make sense to spend lots of money on super low inductance capacitors with
> > >this as a handicap.)
> > >
> > >You would do better by your design by using simple 0603 0r 0402
>capacitors
> > >with two vias per mounting pad. In the bargain, you will avoid making
>your
> > >design single sourced- and imprortant consideration.
> > >
> > >Lee W. Ritchey
> > >Speeding Edge
> > >P. O. Box 2194
> > >Glen Ellen, CA 95442
> > >Phone- 707-568-3983
> > >FAX- 707-568-3504
> > >
> > >I just used the energy it took to be angry to write some blues.
> > >Count Basie
> > >
> > >
> > > > [Original Message]
> > > > From: Larry SMITH <Larry.Smith@xxxxxxx>
> > > > To: <adsurevv@xxxxxxxxx>
> > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > Date: 5/27/2005 2:36:21 PM
> > > > Subject: [SI-LIST] Re: S11 or S21
> > > >
> > > > Virenda - The ESL of a ceramic capacitor is a rather elusive
>parameter.
> > > > It depends a lot on how you define it, how you intend to use it and
>how
> > > > you measure it. In any case, most of the inductance will be in the
> > > > mounting structure for the capacitor and a less significant inductance
> > > > will be associated with the capacitor itself.
> > > >
> > > > A ceramic capacitor might be used as a DC blocking device (AC coupler)
> > > > for high speed serial links. In that case, it is probably in a
> > > > signaling environment with 50 Ohm microstrip traces leading up to the
> > > > pads. For this application, you would probably want to measure the
>ESL
> > > > by mounting it on pads connected to 50 Ohm traces so that the AC
>current
> > > > completes the path between the 50 Ohm traces during the measurement.
>A
> > > > TDR, TDT, VNA S11 or S22 measurement will be able to detect an
>inductive
> > > > discontinuity associated with the mounted capacitor. The inductance
> > > > value might be called ESL.
> > > >
> > > > The same ceramic capacitor might be used in a decoupling application
> > > > where it is tied to Vdd and Gnd planes of a package or PCB. The power
> > > > plane impedance is likely to be much less than 1 Ohm, far different
>than
> > > > a 50 Ohm signaling environment. The capacitor will be connected in
> > > > shunt (parallel) with the planes (rather than in series) so it should
>be
> > > > measured that way. The most interesting frequency band is at series
> > > > resonance (1 to 100 MHz), where the impedance of the capacitor is
> > > > approximately the ESR, (10 mOhm range). S11 measurements do not work
> > > > very well under these conditions because of the inductance of the
> > > > fixture. Even a 1 nH fixture, which is difficult to make, will give
> > > > 62.8 mOhms in series with your capacitor at 10 MHz, 6 times more than
> > > > the impedance you are trying to measure. For that reason, S21 is your
> > > > best bet.
> > > >
> > > > What is the nature of your 2" test board? Is the capacitor mounted in
> > > > series with 50 Ohm traces or is in parallel with power planes? A
>third
> > > > possibility is a continuous 50 Ohm microstrip trace touching one pad
>and
> > > > the other pad shorted to the ground plane below. In this case, the
> > > > capacitor shorts the 50 Ohm trace to ground. Each of these three
> > > > fixtures will give you a different ESL for your capacitor. Actually,
> > > > you are measuring the mounting inductance of the fixture more than you
> > > > are measuring the ESL of the capacitor.
> > > >
> > > > I like to define the ESL of the mounted capacitor in terms of it's
> > > > capacitance and resonant frequency: ESL = 1/((2*pi*f0)^2*C) . The
>ESL
> > > > can be further broken down into the mounting inductance, filler
> > > > inductance at the bottom of the cap and plate inductance. (See Sun
> > > > Microsystems SI documents associated with SI-list for references).
>But
> > > > most of the inductance is probably in the mount unless you have taken
> > > > great effort in your fixture to minimize it.
> > > >
> > > > My major point in writing this email is that ESL is not a very well
> > > > defined parameter and the industry does not have good agreement on how
> > > > it should be measured.
> > > >
> > > > regards,
> > > > Larry Smith
> > > > Sun Microsystems
> > > >
> > > > Virendra wrote:
> > > > > Hello All,
> > > > > I am trying to measure the esl of a ceramic capacitor.
> > > > > I have a test board of 2"x 2" for this. I have SMA
> > > > > connectors connected to two sides of the test board.
> > > > > Now to extract the esl of the capacitor, is it best to
> > > > > measure the S11 or S21.
> > > > > Given that S21 gives lesser measurement errors does it
> > > > > still make sense to measure S21 when the two
> > > > > connectors are 2" apart?
> > > > >
> > > > > thanks in advance,
> > > > > virendra
> > > > >
> > > > >
> > > > >
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