[SI-LIST] Re: S11 or S21

  • From: John Zasio <zasio@xxxxxxxxxxxxxxxxxxx>
  • To: steve weir <weirsi@xxxxxxxxxx>
  • Date: Tue, 31 May 2005 10:59:19 -0700

Steve,
I am not embarrassed at all. I have presented data measured on
small test boards and used this data to design systems. The
data from single capacitor measurement was used to design the
impedance profile for many large high power boards. It has been
verified with measurements of the impedance profile on these
boards and more importantly on the power plane noise on
functioning hardware. I have never had a single instance of a
system that did not function because of power supply noise or
signal integrity issues.

This forum is to allow experienced engineers like you and I
to offer advice to those who have less experience. I feel like it
is pay back to all those that have helped me. My advice is
to not trust manufacturers datasheets for all the parameters
needed to build high speed systems. Build test structures to
create the models necessary to do your design.

The manufacturers of capacitors generally present accurate data
on the equivalent series inductance. However they are giving you
the difference between a short across their test fixture and the
inductance with the capacitor replacing the short. This is of
little interest to me. What I care about is how the capacitor
functions on PC boards with the same stackup that I must use for
the product. The via inductance on typical boards is much higher
than the manufacturer's value for the capacitor and this board via
inductance dominates.

I have chosen not to use the X2Y capacitors on my boards. For
me they do not meet my requirements as well as 0402 devices.
I admit that it takes 50% more devices but they are smaller than
the X2Y, cost less, and use same total number of vias. You
present an opinion that the X2Y is the right choice and only
choice. I present an opinion that there are other choices and I
think the people asking for advice should understand that there
is more than one solution.

John Zasio

steve weir wrote:

> John, as we discussed, there are both problems with your measurement 
> methods and your conclusions that are evident based on your writings. 
>
> Let's take a look at your reported data points as reported in Lee's 
> and your book:
>
> I have formatted the following table using spaces so just view in a 
> monospace font like courier new to get the columns to line up:
>
> Table values reported from "Right the First Time" Ritchey w/ Zasio pp 
> 143 Table 35.1:
> =====================================
> Vendor      AVX     AVX     AVX      |
> Case        0603    0603    0612 IDC |
> Cap         100nF   100nF   100nF    |
> Vias        2       4       8        |
> Cesl        950pH   460pH   151pH    | 
>                                      |          Extracted
> Via length  ESL     ESL     ESL      |      L/mil   L/mil   L/mil
> 13.5        1190    580     230      |     
> 28.8        1460    720     310      |       17.6     9.2     5.2
> 62.5        2060    1010    500      |       17.8     8.6     5.6
> 77.5        2330    1150    580      |       18.0     9.3     5.3
>                                      |Ave    17.8     9.0     5.4
>                                      |*vias  35.6    36.0    43.2
> =================================================================
>                                                                               
>                                     
>
>
> From this data, you offered the conclusion:
>
> "The Length Factor (Lf) of 35.5 pH/mil works for all 0603 size 
> capacitors with either two or four vias." 
>
> In reference to the equation:
>
> Cesl = ESLcap + Via_length * Length_Factor / Number_of_vias
>
> In other words, vias do not interact.
>
> Your first clue that something is wrong should have been the notion 
> that four vias mounted on the corners of a 50mil / side box should 
> exhibit 1/2 the inductance of just one pair on one side ( pg 142, 
> fig.35.5 ).  Solenoids still work even if loosely wound.
>
> Your second clue that there is a problem with your beliefs, data or 
> both should have been that inductance of the interdigitated vias on 
> AVX IDC went up instead of down compared to conventional capacitors, 
> without any further explanation. 
>
> Your third clue should have been that your extracted inductance per 
> unit length does not match published and verified derivations, 
> including those readily available as published by Dr. Johnson, which 
> are themselves readily verifiable using a physics text such as 
> Halliday and Resnick to apply the method of Biot and Savart.  You 
> report 35.5pH/mil for 10mil via pairs on 50 mil centers.  The correct 
> value should be about 46.8pH, over 30% higher.  How do you reconcile 
> that your vias should be better than theory?
>
> Your fourth clue should have been that your extraction for the IDC raw 
> component inductance came out 150pH, when those parts as reported by 
> both AVX and independent measurement show up as very close to 60pH.  
>
> So how did your experiments go bad?
>
> First, your fixture, an approx. 4" x 10" board sets the RF source and 
> the receiver close together at the far end of a narrow aspect ratio 
> board, and the target capacitor positions essentially along the length 
> of that board.  This minimizes the incremental transfer impedance 
> changes for the various capacitor positions that you used on 
> approximate 2.5 inch spacings. 
>
> Second, the tests that you did use only a single capacitor at a time 
> on that platform with 3mil dielectric plane pairs.  The impedance of 
> the mounted capacitors is so high compared to the capacitors that you 
> erroneously concluded that they contribute a negligible amount of 
> impedance.  This is true for the tests, but is false for any system 
> requiring anything but an late 1980's early 1990s impedance profile.
>
> Third, the test fixture attempts to derive inductance values for 
> attachments to planes at various depths, but where apparently, all the 
> planes have been joined together at the RF generator / spectrum 
> analyzer connections in the upper left hand corner of the board.  
> Since there is no pictorial evidence, nor any comment about the issue, 
> I doubt that you did anything to either insure that the instrument 
> connections to each plane formed contiguous transmission lines, nor 
> found a way to deembed the parasitics of those attachments.  This 
> means that your measurements were colored in two important ways:
>
> 1. The parasitic inductance of the attachments increased the apparent 
> insertion loss above the actual values, and tended to equalize all of 
> the measurements.
> 2. The measurements reflected the distance from the uppermost plane in 
> the entire board to the uppermost plane that any given capacitor 
> attached to.
>
> Your experiments measured lots of combined effects that you failed to 
> account for, leading you to very faulty conclusions.  For unknown 
> reasons you discounted, or ignored the prominent warnings readily 
> visible in your data.  I hope for your sake and the sake of customers 
> of you or Lee that your faulty beliefs and conclusions have not been 
> relied upon. 
>
> I am sorry if all this is embarrassing to you in a public forum, but 
> as you know, I have offered multiple times to show both you and Lee 
> how you have gone wrong privately.
>
> Steve.
>
> At 09:11 AM 5/28/2005 -0700, John Zasio wrote:
>
>> Steve,
>>
>> I have come to the opposite conclusion than you in regard to the 
>> benefit of
>> IDC or X2Y capacitors for decoupling. In order to obtain the data for my
>> conclusions I build small multi-layer test boards and measure several 
>> caps
>> with varying via length to the power planes. What is important to me 
>> is the
>> total effective inductance of the mounted capacitor.
>>
>> The most recent test board has 26 layers and is 100 mils thick. I mounted
>> 0402 capacitors with 4 vias and X2Y capacitors with 6 vias. Power plane
>> one (PP1) is closest to the surface of the board and PP6 is near the 
>> bottom.
>> Measured ESL is as follows:
>>
>> Plane     0402        X2Y
>> PP1       480pH     350pH
>> PP6       880pH     650pH
>>
>> The measured data shows that a single X2Y capacitor is better than a 
>> single
>> 0402 but the total effective inductance vs via count is better for 
>> the 0402. If
>> you use three 0402 capacitors in parallel (12 vias) the ESL is 160pH. Two
>> X2Y capacitors in parallel (12 vias) has an ESL of 175pH on my board.
>>
>> There are four other factors that influence my preference of using 
>> the 0402.
>> 1. The rectangular via pattern for the 0402 is much better for 
>> internal signal
>>     layer routing.
>> 2. The smaller footprint of the 0402 is easier to place on the PCB and in
>>     fact can be placed on the opposite side of the board directly 
>> under an
>>     IC using the same vias on a 1.0mm pitch.
>> 3. The cost of the X2Y is about 5x that of the 0402.
>> 4. The 0402 is manufactured in high volume by all suppliers of ceramic
>>     capacitors while the X2Y has limited sources.
>>
>> John Zasio
>>
>>
>> Lee Ritchey wrote:
>>
>>>
>>>Steve,
>>>
>>>You haven't burst my baloon.  I have paid attention to John Zasio's
>>>work in
>>>the book we cowrote.  Figure 34.10 on page 138 shows four different
>>>sets of
>>>meaurements of capacitors mounted various ways, including IDCs. 
>>>These
>>>measurements are taken with the capacitors hooked up to the first two
>>>planes below the surface of the PCB.  Yes, the IDC is electrically
>>>better,
>>>but not enough so as to warrant their extra cost.  Again, this
>>>similar
>>>performance is due to mounting inductance.  When these capacitors
>>>are
>>>connected to planes lower in the PCB, the result is even worse. 
>>>
>>>When X2Y capacitors are mounted in a similar way, the results are also
>>>similar.  Yes, we have done those tests, too.  Perhaps John
>>>would care to
>>>chime in here.
>>>
>>>
>>>
>>>Lee W. Ritchey
>>>Speeding Edge
>>>P. O. Box 2194
>>>Glen Ellen, CA 95442
>>>Phone- 707-568-3983
>>>FAX-    707-568-3504
>>>
>>>I just used the energy it took to be angry to write some blues.
>>>Count Basie
>>>
>>>
>>> 
>>>      
>>>
>>>>
>>>>[Original Message]
>>>>From: steve weir
>>>><weirsi@xxxxxxxxxx> <mailto:weirsi@xxxxxxxxxx>
>>>>To:
>>>><leeritchey@xxxxxxxxxxxxx> <mailto:leeritchey@xxxxxxxxxxxxx>;
>>>>Larry Smith
>>>><larry.smith@xxxxxxx> <mailto:larry.smith@xxxxxxx>;
>>>>   
>>>>        
>>>>
>>>
>>><adsurevv@xxxxxxxxx> <mailto:adsurevv@xxxxxxxxx>
>>> 
>>>      
>>>
>>>>
>>>>Cc:
>>>><si-list@xxxxxxxxxxxxx> <mailto:si-list@xxxxxxxxxxxxx>
>>>>Date: 5/27/2005 3:56:39 PM
>>>>Subject: Re: [SI-LIST] Re: S11 or S21
>>>>
>>>>Lee, I hate to burst your balloon, but you would do well to pay attention 
>>>>to the test data that John Zasio presents in your book "Right the
>>>>First 
>>>>Time"  If I recall correctly his comparison of various mounted
>>>>capacitor 
>>>>performance including 0612 IDCs may be found in Chapter 36 ( might be 
>>>>35
>>>>   
>>>>        
>>>>
>>>
>>>or 
>>> 
>>>      
>>>
>>>>
>>>>37 ).  While it is true that vias, and particularly long vias
>>>>diminish
>>>>   
>>>>        
>>>>
>>>
>>>the 
>>> 
>>>      
>>>
>>>>
>>>>advantage of low inductance capacitors, on average IDCs and X2Ys
>>>>make
>>>>   
>>>>        
>>>>
>>>
>>>more 
>>> 
>>>      
>>>
>>>>
>>>>efficient use of vias than doubling up vias on conventional
>>>>caps.  This
>>>>   
>>>>        
>>>>
>>>
>>>can 
>>> 
>>>      
>>>
>>>>
>>>>also be determined from John's data in your book.  Doubling up
>>>>vias on 
>>>>conventional caps reduces conventional cap count but increases total vias 
>>>>and blocked routes compared to simply using conventional caps, or
>>>>   
>>>>        
>>>>
>>>
>>>properly 
>>> 
>>>      
>>>
>>>>
>>>>applying low inductance caps.
>>>>
>>>>While IDCs are quite expensive, other ultalow inductance capacitors, like 
>>>>X2Ys are not.  The performance advantages in terms of component
>>>>count, 
>>>>vias, and overall cost can be found in several of my presentations 
>>>>available at the X2Y web site
>>>>www.x2y.com <http://www.x2y.com>, and the Teraspeed web site 
>>>>www.teraspeed.com <http://www.teraspeed.com>, including my
>>>>DesignCon 2005 paper "High Performance
>>>>   
>>>>        
>>>>
>>>
>>>FPGA 
>>> 
>>>      
>>>
>>>>
>>>>Bypass Networks".
>>>>
>>>>As to whether IDCs which do cost a lot, Teraspeed has customers who do
>>>>   
>>>>        
>>>>
>>>
>>>not 
>>> 
>>>      
>>>
>>>>
>>>>have X2Y on their AVL, and for whom IDC provides superior value,
>>>>because 
>>>>space, and not raw component cost is the premium value.
>>>>
>>>>Steve
>>>>At 02:53 PM 5/27/2005 -0700, Lee Ritchey wrote:
>>>>   
>>>>        
>>>>
>>>>>
>>>>>Virenda,
>>>>>
>>>>>To add to what Larry has said, if you are interested in the parasitic
>>>>>inductance of a capacitor as it relates to using the part as part of
>>>>>your
>>>>>power bypassing, it will turn out that the mounting inductance will
>>>>>dominate over the parts parasitic inductance.  Part of this is due
>>>>>to the
>>>>>inductance of the vias needed to connect the capacitor to the power
>>>>>     
>>>>>          
>>>>>
>>>
>>>planes
>>> 
>>>      
>>>
>>>>>
>>>>>it is used with and part of it is due to the size of the mounting
>>>>>     
>>>>>          
>>>>>
>>>
>>>structure
>>> 
>>>      
>>>
>>>>>
>>>>>needed to solder the part to the PCB.
>>>>>
>>>>>Tests have shown that once you have to reach planes deeper into the PCB
>>>>>than 10 or so mils, the value of ultra low inductance parts such as IDC
>>>>>     
>>>>>          
>>>>>
>>>
>>>is
>>> 
>>>      
>>>
>>>>>
>>>>>masked to the point they are not worth the extra cost.  (The
>>>>>inductand of
>>>>>vias is about 35 pH per mil of length.  With two of these, reaching
>>>>>just
>>>>>     
>>>>>          
>>>>>
>>>
>>>20
>>> 
>>>      
>>>
>>>>>
>>>>>mils into the PCB results in almost .7 nH just from mounting vias. 
>>>>>     
>>>>>          
>>>>>
>>>
>>>Doesn't
>>> 
>>>      
>>>
>>>>>
>>>>>make sense to spend lots of money on super low inductance capacitors
>>>>>with
>>>>>this as a handicap.)
>>>>>
>>>>>You would do better by your design by using simple 0603 0r 0402
>>>>>     
>>>>>          
>>>>>
>>>
>>>capacitors
>>> 
>>>      
>>>
>>>>>
>>>>>with two vias per mounting pad.  In the bargain, you will avoid
>>>>>making
>>>>>     
>>>>>          
>>>>>
>>>
>>>your
>>> 
>>>      
>>>
>>>>>
>>>>>design single sourced- and imprortant consideration.
>>>>>
>>>>>Lee W. Ritchey
>>>>>Speeding Edge
>>>>>P. O. Box 2194
>>>>>Glen Ellen, CA 95442
>>>>>Phone- 707-568-3983
>>>>>FAX-    707-568-3504
>>>>>
>>>>>I just used the energy it took to be angry to write some blues.
>>>>>Count Basie
>>>>>
>>>>>
>>>>>     
>>>>>          
>>>>>
>>>>>>
>>>>>>[Original Message]
>>>>>>From: Larry SMITH
>>>>>><Larry.Smith@xxxxxxx> <mailto:Larry.Smith@xxxxxxx>
>>>>>>To: <adsurevv@xxxxxxxxx> <mailto:adsurevv@xxxxxxxxx>
>>>>>>Cc:
>>>>>><si-list@xxxxxxxxxxxxx> <mailto:si-list@xxxxxxxxxxxxx>
>>>>>>Date: 5/27/2005 2:36:21 PM
>>>>>>Subject: [SI-LIST] Re: S11 or S21
>>>>>>
>>>>>>Virenda - The ESL of a ceramic capacitor is a rather elusive
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>parameter.
>>> 
>>>      
>>>
>>>>>>
>>>>>> It depends a lot on how you define it, how you intend to use
>>>>>>it and
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>how
>>> 
>>>      
>>>
>>>>>>
>>>>>>you measure it.  In any case, most of the inductance will be in
>>>>>>the
>>>>>>mounting structure for the capacitor and a less significant inductance
>>>>>>will be associated with the capacitor itself.
>>>>>>
>>>>>>A ceramic capacitor might be used as a DC blocking device (AC coupler)
>>>>>>for high speed serial links.  In that case, it is probably in a
>>>>>>signaling environment with 50 Ohm microstrip traces leading up to the
>>>>>>pads.  For this application, you would probably want to measure 
>>>>>>the
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>ESL
>>> 
>>>      
>>>
>>>>>>
>>>>>>by mounting it on pads connected to 50 Ohm traces so that the AC
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>current
>>> 
>>>      
>>>
>>>>>>
>>>>>>completes the path between the 50 Ohm traces during the measurement. 
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>A
>>> 
>>>      
>>>
>>>>>>
>>>>>>TDR, TDT, VNA S11 or S22 measurement will be able to detect an
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>inductive
>>> 
>>>      
>>>
>>>>>>
>>>>>>discontinuity associated with the mounted capacitor.  The
>>>>>>inductance
>>>>>>value might be called ESL.
>>>>>>
>>>>>>The same ceramic capacitor might be used in a decoupling application
>>>>>>where it is tied to Vdd and Gnd planes of a package or PCB.  The
>>>>>>power
>>>>>>plane impedance is likely to be much less than 1 Ohm, far different
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>than
>>> 
>>>      
>>>
>>>>>>
>>>>>>a 50 Ohm signaling environment.  The capacitor will be
>>>>>>connected in
>>>>>>shunt (parallel) with the planes (rather than in series) so it should
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>be
>>> 
>>>      
>>>
>>>>>>
>>>>>>measured that way.  The most interesting frequency band is at
>>>>>>series
>>>>>>resonance (1 to 100 MHz), where the impedance of the capacitor is
>>>>>>approximately the ESR, (10 mOhm range).  S11 measurements do not
>>>>>>work
>>>>>>very well under these conditions because of the inductance of the
>>>>>>fixture.  Even a 1 nH fixture, which is difficult to make, will
>>>>>>give
>>>>>>62.8 mOhms in series with your capacitor at 10 MHz, 6 times more than
>>>>>>the impedance you are trying to measure.  For that reason, S21 is
>>>>>>your
>>>>>>best bet.
>>>>>>
>>>>>>What is the nature of your 2" test board?  Is the capacitor
>>>>>>mounted in
>>>>>>series with 50 Ohm traces or is in parallel with power planes?  A
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>third
>>> 
>>>      
>>>
>>>>>>
>>>>>>possibility is a continuous 50 Ohm microstrip trace touching one
>>>>>>pad
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>and
>>> 
>>>      
>>>
>>>>>>
>>>>>>the other pad shorted to the ground plane below.  In this case,
>>>>>>the
>>>>>>capacitor shorts the 50 Ohm trace to ground.  Each of these three
>>>>>>fixtures will give you a different ESL for your capacitor. 
>>>>>>Actually,
>>>>>>you are measuring the mounting inductance of the fixture more than you
>>>>>>are measuring the ESL of the capacitor.
>>>>>>
>>>>>>I like to define the ESL of the mounted capacitor in terms of it's
>>>>>>capacitance and resonant frequency:  ESL = 1/((2*pi*f0)^2*C) . 
>>>>>>The
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>ESL
>>> 
>>>      
>>>
>>>>>>
>>>>>>can be further broken down into the mounting inductance, filler
>>>>>>inductance at the bottom of the cap and plate inductance.  (See 
>>>>>>Sun
>>>>>>Microsystems SI documents associated with SI-list for references). 
>>>>>>       
>>>>>>            
>>>>>>
>>>
>>>But
>>> 
>>>      
>>>
>>>>>>
>>>>>>most of the inductance is probably in the mount unless you have
>>>>>>taken
>>>>>>great effort in your fixture to minimize it.
>>>>>>
>>>>>>My major point in writing this email is that ESL is not a very well
>>>>>>defined parameter and the industry does not have good agreement on how
>>>>>>it should be measured.
>>>>>>
>>>>>>regards,
>>>>>>Larry Smith
>>>>>>Sun Microsystems
>>>>>>
>>>>>>Virendra wrote:
>>>>>>       
>>>>>>            
>>>>>>
>>>>>>>
>>>>>>>Hello All,
>>>>>>>I am trying to measure the esl of a ceramic capacitor.
>>>>>>> I have a test board of 2"x 2" for this.  I have 
>>>>>>>SMA
>>>>>>>connectors connected to two sides of the test board.
>>>>>>>Now to extract the esl of the capacitor, is it best to
>>>>>>>measure the S11 or S21.
>>>>>>>Given that S21 gives lesser measurement errors does it
>>>>>>>still make sense to measure S21 when the two
>>>>>>>connectors are 2" apart?
>>>>>>>
>>>>>>>thanks in advance,
>>>>>>>virendra
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>__________________________________
>>>>>>>Do you Yahoo!?
>>>>>>>Yahoo! Mail - Helps protect you from nasty viruses.
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