Posts for si-list, 06-2005

Browse: Last Month: 05-2005 Main Archive Page Next Month: 07-2005

» [SI-LIST] Re: Agilent TDR Normalization Questions -
» [SI-LIST] Re: Perl scripts for Hspice -
» [SI-LIST] Perl scripts for Hspice -
» [SI-LIST] Re: Substrate board impedance added to driver impedance for total output impedance of driver -
» [SI-LIST] Re: Substrate board impedance added to driver impedance for total output impedance of driver -
» [SI-LIST] Substrate board impedance added to driver impedance for total output impedance of driver -
» [SI-LIST] HyperLynx Technical Marketing Engineer -
» [SI-LIST] Re: Agilent TDR Normalization Questions -
» [SI-LIST] Re: Agilent TDR Normalization Questions -
» [SI-LIST] Re: Agilent TDR Normalization Questions -
» [SI-LIST] Re: Agilent TDR Normalization Questions -
» [SI-LIST] Agilent TDR Normalization Questions -
» [SI-LIST] Re: Data Bus termination -
» [SI-LIST] SI position available at Broadcom -
» [SI-LIST] FW: *-AMS language versions in IBIS -
» [SI-LIST] Re: Data Bus termination -
» [SI-LIST] Re: Data Bus termination -
» [SI-LIST] *-AMS language versions in IBIS -
» [SI-LIST] Intel Job Opportunities -
» [SI-LIST] Re: Tip and Ring routing consideration -
» [SI-LIST] Re: Fixing a black pad -
» [SI-LIST] Re: Fixing a black pad -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Tip and Ring routing consideration -
» [SI-LIST] Re: Tip and Ring routing consideration -
» [SI-LIST] Tip and Ring routing consideration -
» [SI-LIST] Re: Fixing a black pad -
» [SI-LIST] Re: Data Bus termination -
» [SI-LIST] Re: Data Bus termination -
» [SI-LIST] Data Bus termination -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Single crystal driving two different inputs of a chip -
» [SI-LIST] Single crystal driving two different inputs of a chip -
» [SI-LIST] Re: Fixing a black pad -
» [SI-LIST] Re: Fixing a black pad -
» [SI-LIST] Fixing a black pad -
» [SI-LIST] Re: Power problem -
» [SI-LIST] Re: Power problem -
» [SI-LIST] Power problem -
» [SI-LIST] Re: Thesis (Eliminating package resonances due to standing waves) -
» [SI-LIST] Looking for simple script to parse and reformat IBIS .pkg file data -
» [SI-LIST] Re: Thesis (Eliminating package resonances due to standing waves) -
» [SI-LIST] Re: Thesis (Eliminating package resonances due to standing waves) -
» [SI-LIST] Re: Thesis (Eliminating package resonances due to standing waves) -
» [SI-LIST] Re: Thesis (Eliminating package resonances due to stand ing waves) -
» [SI-LIST] Re: SI Package Analysis tools -
» [SI-LIST] Re: SI Package Analysis tools -
» [SI-LIST] Re: SI Package Analysis tools -
» [SI-LIST] Thesis (Eliminating package resonances due to standing waves) -
» [SI-LIST] SI Package Analysis tools -
» [SI-LIST] Re: Impedance Mismatch due to neck down -
» [SI-LIST] Re: Impedance Mismatch due to neck down -
» [SI-LIST] R: Impedance Mismatch due to neck down -
» [SI-LIST] Re: Impedance Mismatch due to neck down -
» [SI-LIST] Impedance Mismatch due to neck down -
» [SI-LIST] Crosstalk Paper -
» [SI-LIST] Crosstalk, part deux -
» [SI-LIST] Jitter Netseminar. -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Signal Integrity Engineering Position at Xilinx -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Re: why do one need PRBS Rx AND Tx? -
» [SI-LIST] Re: why do one need PRBS Rx AND Tx? -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Re: why do one need PRBS Rx AND Tx? -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Re: why do one need PRBS Rx AND Tx? -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] why do one need PRBS Rx AND Tx? -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] Re: digital to analogue noise coupling -
» [SI-LIST] digital to analogue noise coupling -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] Re: basic question regarding inductor before Vcc -
» [SI-LIST] basic question regarding inductor before Vcc -
» [SI-LIST] Impedance Webinar -
» [SI-LIST] Re: Propagation delay -
» [SI-LIST] Re: the "big V" approach -
» [SI-LIST] the "big V" approach -
» [SI-LIST] Siganl Integrity Engineer opening with Force10 Networks -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: Search for the paper about minimum BGA pad size in PCB -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: Propagation delay -
» [SI-LIST] Re: Search for the paper about minimum BGA pad size in PCB -
» [SI-LIST] Propagation delay -
» [SI-LIST] Re: Impedence for differential -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Impedence for differential -
» [SI-LIST] Re: Search for the paper about minimum BGA pad size in PCB -
» [SI-LIST] Re: Search for the paper about minimum BGA pad size in PCB -
» [SI-LIST] Search for the paper about minimum BGA pad size in PCB -
» [SI-LIST] Re: PCI Express Add-in Card -
» [SI-LIST] Effective inductance calculation of a 3-wire system -
» [SI-LIST] Re: Effective inductance calculation of a 3-wire system -
» [SI-LIST] PCI Express Add-in Card -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] Re: To remove reference planes under the gold finger areas -
» [SI-LIST] To remove reference planes under the gold finger areas -
» [SI-LIST] Re: Effective inductance calculation of a 3-wire system -
» [SI-LIST] Re: Eye diagram measurement -
» [SI-LIST] Effective inductance calculation of a 3-wire system -
» [SI-LIST] Surge current -
» [SI-LIST] How to evaluate the quality of xDSL signal channel accurately? -
» [SI-LIST] Ferrite loaded transmission lines -
» [SI-LIST] Re: Stable Pulse width generation -
» [SI-LIST] Re: Stable Pulse width generation -
» [SI-LIST] Stable Pulse width generation -
» [SI-LIST] Re: Variations in TDR from Via Tuning -
» [SI-LIST] Re: DDR2 at speeds faster than DDR2-533 -
» [SI-LIST] Reference Plane under PCI edge finger pads -
» [SI-LIST] Re: Need for parallell termination to Vtt on DDR SDRAM? -
» [SI-LIST] Need for parallell termination to Vtt on DDR SDRAM? -
» [SI-LIST] Re: Variations in TDR from Via Tuning -
» [SI-LIST] Re: Scale option in Hspice -
» [SI-LIST] Re: Variations in TDR from Via Tuning -
» [SI-LIST] Re: Variations in TDR from Via Tuning -
» [SI-LIST] Variations in TDR from Via Tuning -
» [SI-LIST] Re: Measuring eyediagram worsecase width and height -
» [SI-LIST] Measuring eyediagram worsecase width and height -
» [SI-LIST] Re: Scale option in Hspice -
» [SI-LIST] Pkg Power Plane Analysis -
» [SI-LIST] unsubscribe' -
» [SI-LIST] Question on SPI/SFI-5 -
» [SI-LIST] SUBSCRIBE -
» [SI-LIST] Signal Integrity position available - ServerEngines - Santa Clara, CA -
» [SI-LIST] Re: DFE -
» [SI-LIST] BGA Crosstalk Tech-Online TODAY! -
» [SI-LIST] FW: Re: Using Matlab for SERDES simulations -
» [SI-LIST] Re: DDR2 at speeds faster than DDR2-533 -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Re: Far-end crosstalk over long PCB trace -
» [SI-LIST] Far-end crosstalk over long PCB trace -
» [SI-LIST] via impedance SE and DIFF -
» [SI-LIST] Re: DDR2 at speeds faster than DDR2-533 -
» [SI-LIST] DDR2 at speeds faster than DDR2-533 -
» [SI-LIST] Re: DFE -
» [SI-LIST] Re: DFE -
» [SI-LIST] DFE -
» [SI-LIST] Length of the 1.8V LVCMOS - signals at 212MHZ DDR -
» [SI-LIST] Re: Jitter on serial data buses -
» [SI-LIST] Re: Jitter on serial data buses -
» [SI-LIST] Re: Jitter on serial data buses -
» [SI-LIST] w element table model - methodology -
» [SI-LIST] Re: Using Matlab for SERDES simulations -
» [SI-LIST] Re: Using Matlab for SERDES simulations -
» [SI-LIST] Re: Jitter on serial data buses -
» [SI-LIST] Re: differential DJ and RJ -
» [SI-LIST] differential DJ and RJ -
» [SI-LIST] Re: Can we run DDR2 devices below 125 Mhz clock frequency -
» [SI-LIST] Xilinx LVDS and SCSI -
» [SI-LIST] New version of Vector Fitting available -
» [SI-LIST] near and far end crosstalk data derived from IEC test -
» [SI-LIST] Job Opening. -
» [SI-LIST] Can we run DDR2 devices below 125 Mhz clock frequency -
» [SI-LIST] HW openings at Silverback Systems -
» [SI-LIST] Re: Noise measurement -
» [SI-LIST] 74LVC125A with pull up resistors in the input -
» [SI-LIST] Noise measurement -
» [SI-LIST] Re: Getting a Clean eye in HSPICE -
» [SI-LIST] Getting a Clean eye in HSPICE -
» [SI-LIST] Re: VHDL-AMS models in automotive industry -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: S11 or S21 -
» [SI-LIST] Re: FW: Re: Scale option in Hspice -
» [SI-LIST] SI Engineer position in Altera -
» [SI-LIST] Re: Signal Integrity with Protel 2004 -
» [SI-LIST] Re: Jitter on serial data buses -
» [SI-LIST] Jitter on serial data buses -
» [SI-LIST] Signal Integrity with Protel 2004 -
» [SI-LIST] FW: Re: Scale option in Hspice -
» [SI-LIST] Re: Scale option in Hspice -