Posts for si-list, 05-2002

Browse: Last Month: 04-2002 Main Archive Page Next Month: 06-2002

» [SI-LIST] Re: list server outage -
» [SI-LIST] Graduating student looking for position -
» [SI-LIST] list server outage -
» [SI-LIST] Re: Errata Sheet for Wadell's "Transmission Line Design Handbook" -
» [SI-LIST] Re: Errata Sheet for Wadell's "Transmission Line Design Handbook" -
» [SI-LIST] Re: Decoupling capacitors - mesh density -
» [SI-LIST] Errata Sheet for Wadell's "Transmission Line Design Handbook" -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] PCI CLOCK AND DATA IN HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] PCI Timing Q? -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Using W-element in HSPICE -
» [SI-LIST] Re: Decoupling capacitors - mesh density -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: PCI Timing Q? -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: PCI Timing Q? -
» [SI-LIST] Re: PCI Timing Q? -
» [SI-LIST] Re: PCI Timing Q? -
» [SI-LIST] Re: PCI Timing Q? -
» [SI-LIST] PCI Timing Q? -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: Decoupling capacitors - mesh density -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: [SI-LIST]: Design a shielded differential line -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON EMC - NEW VENUE! NEW CALL FORPAPERS -
» [SI-LIST] [SI-LIST]: Design a shielded differential line -
» [SI-LIST] FPC Cable Modeling -
» [SI-LIST] Sweep voltage source for EMI study -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Waveform Correlation -
» [SI-LIST] Re: Entry level RF book -
» [SI-LIST] Re: Waveform Correlation -
» [SI-LIST] Waveform Correlation -
» [SI-LIST] Re: FWD: Signal Integrity Position -
» [SI-LIST] Re: FWD: Signal Integrity Position -
» [SI-LIST] FWD: Signal Integrity Position -
» [SI-LIST] Re: Attaching coax cable to board -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Attaching coax cable to board -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Resistivity of Tin/lead Plating -
» [SI-LIST] Re: Info on Capacitive loading of devices -
» [SI-LIST] Info on Capacitive loading of devices -
» [SI-LIST] [Fwd: Entry level RF book] -
» [SI-LIST] Re: Pole/Zero Extraction from measured S-parameter -
» [SI-LIST] Re: Entry level RF book -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: problems encountered extracting radiation losses -
» [SI-LIST] Re: PCIX AND Tprop -
» [SI-LIST] Re: PCIX AND Tprop -
» [SI-LIST] PCIX AND Tprop -
» [SI-LIST] Test -
» [SI-LIST] problems encountered extracting radiation losses -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Resistivity of Tin/lead Plating -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] FW: FW: Wire impedance at HF -
» [SI-LIST] FW: FW: Wire impedance at HF -
» [SI-LIST] FW: Wire impedance at HF -
» [SI-LIST] FW: Wire impedance at HF -
» [SI-LIST] Re: Wire impedance at HF -
» [SI-LIST] Re: Wire impedance at HF -
» [SI-LIST] Wire impedance at HF -
» [SI-LIST] Re: s2ibis2 Problem -
» [SI-LIST] s2ibis2 Problem -
» [SI-LIST] Re: Unable to unsubscribe!!!!!!!!!!!!!!! -
» [SI-LIST] Re: FW: Re: Cap discontinuity -
» [SI-LIST] Re: Jitter from Crosstalk -
» [SI-LIST] Unable to unsubscribe!!!!!!!!!!!!!!! -
» [SI-LIST] Re: Labelling waveforms in XTK -
» [SI-LIST] Jitter from Crosstalk -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] FW: Re: Cap discontinuity -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Labelling waveforms in XTK -
» [SI-LIST] a signal integrity problem -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Cross-talk, which one is bigger? -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Cross-talk, which one is bigger? -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: IBIS Model for a Tri_State Pin -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Signal Integrity related papers on SiQual's website -
» [SI-LIST] Re: Cap discontinuity -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Re: Common Mode vs. Even Mode -
» [SI-LIST] Cap discontinuity -
» [SI-LIST] Common Mode vs. Even Mode -
» [SI-LIST] IBIS Model for a Tri_State Pin -
» [SI-LIST] Re: bit sequence generator for SPICE -
» [SI-LIST] Re: Propagation velocity vs. temperature in PCB traces -
» [SI-LIST] Re: .NET Statements in HSPICE for S-Parameters -
» [SI-LIST] Propagation velocity vs. temperature in PCB traces -
» [SI-LIST] bit sequence generator for SPICE -
» [SI-LIST] Announcement -
» [SI-LIST] Re: Two layer board impedance calculation -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Solder & Paste Mask Properties -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Differential noise -
» [SI-LIST] Re: Solder & Paste Mask Properties -
» [SI-LIST] Differential noise -
» [SI-LIST] Re: Sr. SI opportunity -
» [SI-LIST] Two layer board impedance calculation -
» [SI-LIST] Re: .NET Statements in HSPICE for S-Parameters -
» [SI-LIST] Sr. SI opportunity -
» [SI-LIST] DDR SDRAM 857 CLOCK DRIVER -
» [SI-LIST] Re: Effect of Driving current -
» [SI-LIST] Effect of Driving current -
» [SI-LIST] Signal Integrity Seminar, May 21, 2002, Boxborough Massachusetts -
» [SI-LIST] Solder & Paste Mask Properties -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: .NET Statements in HSPICE for S-Parameters -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe outp -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Eye diagrams in XTK on PC -
» [SI-LIST] Re: loosely vs tightly coupled differential pairs -
» [SI-LIST] Re: .NET Statements in HSPICE for S-Parameters -
» [SI-LIST] .NET Statements in HSPICE for S-Parameters -
» [SI-LIST] SI Engineer - Available -
» [SI-LIST] Re: Edge Coupled Symmetrical Stripline Questions -
» [SI-LIST] loosely vs tightly coupled differential pairs -
» [SI-LIST] Re: Eye diagrams in XTK on PC -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Edge Coupled Symmetrical Stripline Questions -
» [SI-LIST] Eye diagrams in XTK on PC -
» [SI-LIST] Re: Frequency criterion in power plane_Power integr ity -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe outputfiles -
» [SI-LIST] Re: Anyone with DDR2 experience? -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Limiting number of nodes in HSPICE .probe output files -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Frequency criterion in power plane_Power integr ity -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Re: Board via characteristics (fwd) -
» [SI-LIST] Board via characteristics (fwd) -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Anyone with DDR2 experience? -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Ccomp in HSPICE -
» [SI-LIST] Re: Stub Definition -
» [SI-LIST] Re: DDR SDRAM -
» [SI-LIST] Re: Stub Definition -
» [SI-LIST] Re: DDR SDRAM -
» [SI-LIST] Re: Package Resonance -
» [SI-LIST] DDR SDRAM -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Ccomp in HSPICE -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Package Resonance -
» [SI-LIST] Re: Stub Definition -
» [SI-LIST] Re: Stub Definition -
» [SI-LIST] Stub Definition -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: 3D Field Solvers -
» [SI-LIST] 3D Field Solvers -
» [SI-LIST] Re: [Crosstalk calculation] -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: [Crosstalk calculation] -
» [SI-LIST] Re: Ccomp in HSPICE -
» [SI-LIST] Re: Ccomp in HSPICE -
» [SI-LIST] Re: Voltage droop analysis_ load current model -
» [SI-LIST] Decoupling capacitors -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Voltage droop analysis_ load current model -
» [SI-LIST] [Crosstalk calculation] -
» [SI-LIST] Ccomp in HSPICE -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: Frequency criterion in power plane_Power integrity -
» [SI-LIST] Re: Voltage droop analysis_ load current model -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] DDR DRAM -
» [SI-LIST] Re: looking for (differential) crosstalk calculator onthe web -
» [SI-LIST] differential noise -
» [SI-LIST] looking for (differential) crosstalk calculator on the web -
» [SI-LIST] Limits of Wide Band Match to Reactive Impedances -
» [SI-LIST] Re: looking for (differential) crosstalk calculator on the web -
» [SI-LIST] SJ/ Boston-Sr SI FAE's Needed...Ref fees paid! -
» [SI-LIST] To the list administrator -
» [SI-LIST] S-parameter simulation in NSpice -
» [SI-LIST] signal integrity in circuit pack development process -
» [SI-LIST] Re: Serpentine/Spiral Lines (was Re: Trace Bends) -
» [SI-LIST] Re: Diff 2 Load -
» [SI-LIST] Re: Serpentine/Spiral Lines (was Re: Trace Bends) -
» [SI-LIST] Re: Serpentine/Spiral Lines (was Re: Trace Bends) -
» [SI-LIST] Diff 2 Load -
» [SI-LIST] Design rule on immunity not effective -
» [SI-LIST] Re: Serpentine/Spiral Lines (was Re: Trace Bends) -
» [SI-LIST] Serpentine/Spiral Lines (was Re: Trace Bends) -
» [SI-LIST] Re: Trace Bends -