[SI-LIST] Re: PCI Timing Q?
- From: James_R_Jones@xxxxxxxx
- To: brahim@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 29 May 2002 10:07:55 -0500
Brahim,
My understanding of PCI is that the specification calls for a common clock
architecture. The driving component will output some data synchronous to
the common clock (common clock arrives at all components simultaneously,
well sort of...). The driver will have some Tco. The receiver has some min
setup time and some min hold time. The setup time equation will include the
min clock period because clk(i+1) is used to latch in the data where clk(i)
is used to drive it. The hold time equation does not include clock period
because the driver latches the next bit at clk (i+1) and the receiver is
still latching in the previous bit at clk(i+1). Make sense?
The bus is bidirectional, which means that it should work the same in either
direction. So once you figure it out one way, it should work the same for
the other direction. When finding trace lengths, obviously you would want
to take the most conservative constraint for flight times.
Hope this helps,
James J.
-----Original Message-----
From: Brahim Koudssi [mailto:brahim@xxxxxxxxxxxx]
Sent: Wednesday, May 29, 2002 9:43 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCI Timing Q?
Dear SI-List members,
I need help in answering two questions related to PCI bus transactions,
the specs. do not tell the whole story.
Tval is measured as the delay time between clk(i) and when the data is
valid, clk(i) precedes the data,
Tval is measured at the driver output.
1. Once the signals, clk and data arrive at the receiver, which clock
samples the data?
Is it clk(i) or clk(i-1)?
2. The clock signal is from a board to the PCI expansion card, how's
the data sampled by a board
when the data is originating from the card?
Thank You,
Brahim koudssi
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