[SI-LIST] Re: PCI Timing Q?
- From: Brahim Koudssi <brahim@xxxxxxxxxxxx>
- To: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
- Date: Wed, 29 May 2002 08:36:22 -0700
Thank You Andrew And James,
We are referring to the same clock, clk(i-1) and clk(i+1), I used clck(i-1)
notation to signify the one that comes right after clk(i),
my mistake, I am thinking of delayed clock cycle relative to clk(i) as being
clk(i-1).
I will use your notation in my next question:
Tval (Max) and Tval (min)
Is Tval(max) measured relative to clk(i) and Tval(min) measured relative to
clk(i+1)?
Thanks again,
Brahim
"Ingraham, Andrew" wrote:
> > Tval is measured as the delay time between clk(i) and when the data is
> > valid, clk(i) precedes the data,
> > Tval is measured at the driver output.
> >
> > 1. Once the signals, clk and data arrive at the receiver, which clock
> > samples the data?
> > Is it clk(i) or clk(i-1)?
>
> Neither. It is clk(i+1), the one that comes next after clk(i).
>
> All PCI transfers go from one clock cycle to the next. On the rising edge of
> clock, outputs start to drive data after a delay of Tval. Shortly (Tsu)
> before the next rising edge of clock, the data that was sent is ready to be
> received by an input.
>
> All this is happening all the time. Data outputs are being driven on all
> clock cycles, and received on all clock cycles, one clock cycle after being
> sent.
>
> > 2. The clock signal is from a board to the PCI expansion card, how's
> > the data sampled by a board
> > when the data is originating from the card?
>
> The clocks are timed to arrive at all devices on the bus at about the same
> time, even those on PCI expansion cards.
>
> The data signals get from the expansion card to the motherboard through the
> PCI connector. The PCI connector makes an electrical connection for all
> signals on the bus. It is the same as if the device on the card was on the
> motherboard, except that the "wires" to/from that device are longer (and
> noisier).
>
> Andy
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