[SI-LIST] Re: DDR SDRAM
- From: "D. C. Sessions" <si-list@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: 09 May 2002 05:45:40 -0700
On Thu, 2002-05-09 at 03:54, Ched-Chang Chai wrote:
>
> Dear SI experts,
> For DDR SDRAM using SSTL_2 signaling, is there any particular reason why the
> parallel termination resistors must be tied to Vtt=Vdd/2?
Any other value introduces rise/fall asymmetries which come out
of your timing budget in a source-synchronous environment.
--
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat. |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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