[SI-LIST] PCI Timing Q?

Dear Brahim,

I wanted to elaborate a little more on what Andy and James already said
about setup and hold times.  In any common clock system, like PCI, you have
to worry about two cases:  1) getting the data from the driver to the
receiver in time for the NEXT clock cycle (setup time) and 2) making sure
the data does not flush through from the driver to the receiver during the
SAME clock cycle (hold time).  The hold time case (also called min path or
early mode) is a little more subtle than the setup time case because it is
not at all dependent on the clock cycle.  Anytime the delay of your drive
chip + interconnect is less than your clock skew + hold time, you have the
potential to latch data TOO EARLY.  This is a worse problem than the setup
time problem because you can't slow the clock down to fix it.

Here are two equations that help me remember how all this works.  They are
written in terms of the PCI spec parameters.

Setup time:  Tval(max) + Tprop(max) + Tsu + Tskew < Tcyc

Hold time:  Tval(min) + Tprop(min) > Tskew + Th

Greg Edlund
Senior Engineer
Electronic Packaging Integration
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@xxxxxxxxxx


From: Brahim Koudssi [mailto:brahim@xxxxxxxxxxxx]
Sent: Wednesday, May 29, 2002 9:43 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCI Timing Q?



Dear SI-List members,

 I need help in answering two questions related to PCI bus transactions,
the specs. do not tell the whole story.

 Tval is measured as the delay time between clk(i) and when the data is
valid, clk(i) precedes the data,
  Tval is measured at the driver output.

  1.  Once the signals, clk and data arrive at the receiver, which clock
samples the data?
       Is it clk(i) or clk(i-1)?

  2.  The clock signal is from a board to the PCI expansion card, how's
the data sampled by  a board
        when the data is originating from the card?


  Thank You,
  Brahim koudssi



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