[SI-LIST] Info on Capacitive loading of devices

HI All, 

We have an ASIC working at 133MHz. Depending on the 
requirement, this device can use 1 - 4 memory devices. 
The device timings are specified for a load of 4 x Cio 
(capacitance of IO pins) always. 

Now the question is this. 

If i put only one memory device (based on one application),
then can i put a  capacitor 3 x Cio value in the path so
as to match the load and thus meet the timings?

If so what is the best place to put this capacitor? at the 
source or at the end of trace? 

If i am putting all four memory devices, what is the best  
termination technology? The device has bidirectional pins. 
Can i split the tracks into four and put 10 ohms and then 
drive the four devices? 

        |-------/\/\/\----------------|\
          |                             |/
        |
  |\____|-------/\/\/\----------------|\
  |/    |                             |/
        |
        |-------/\/\/\----------------|\
        |                             |/
        |
        |-------/\/\/\----------------|\
                                      |/

FYI, The maximum trace length could be upto 6". 

Greately appreciate any reply / pointers 

Thanks in advance
sreejith
Paxonet communications

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