[SI-LIST] Re: Resistivity of Tin/lead Plating
- From: "David Hoover" <dhoovy@xxxxxxxxxxxxx>
- To: <fred@xxxxxxxxxxxxx>, <AdeelM@xxxxxxxxxxxx>
- Date: Thu, 23 May 2002 09:12:32 -0700
Outerlayer Processing:
The standard US process for PCB fab on outerlayers is an
additive/subtractive
process. This means that when the PTH gets plated up, the traces and pads
get
plated up also. In order to achieve the desired .001" in the hole, there is
about
~.0014" plated on the traces and pads. Typical finished copper thickness'
are
about 1.5 oz (~.002" - provided base copper foil was .5 oz <.0007">)
The subtractive portion is when a protective sacrificial etch resist metal
is plated
over the desired pads, traces, and PTHs, then the exposed <unwanted) copper
is
etched away. Usually the outerlayers are Soldermask over bare copper
(SMOBC).
Exposed copper solderable areas (defined by the soldermask images) are hot
air solder leveled (HASL).
Soldermasks:
LPI, dryfilm, and wet masks.
By far the most common, predominate soldermask requested is LPI (Liquid
Photoimageable). The ability for this mask to define small features
(solderball pads,
QFP webs, ...etc.) and provide the gasketing effect for the assembler during
paste stenciling has it the #1 choice for requested and preferred soldermask
ink.
The other masks still have some niche markets requiring them. For example,
burn-in
boards require screened full epoxy wet mask to withstand the high oven
temperatures
for long periods of time. Probe Cards (IC testers) desire thick dryfilm mask
in order to
fully tent all unused holes for extremely high vacuum (or vacuum chuck)
testing.
Wet masks are still used as a defined selective image via plug. Some
fabricators may
use the screened wet mask image for low volume lower technology products.
Reliability of Soldermasks.....
Soldermask inks must meet the requirements of IPC-SM-840. This includes
permanency,
coverage, cure, and adhesion (to name the main few). Compatibility with
surface finishes
along with assembly processes are also a large consideration. Generally LPI
soldermask
meets the OEMs requirements.
Surface Finishes:
1. Panel Gold Plating (Flash Gold) (Or full body plated)
If this is defined as an electroplated finish, it can be available in
both hard and soft
gold. Hard could be used for products like PCMCIA or mini-cards that
have both
solderable requirements and some plug in edge fingers. Soft gold would
be for
only solderable images or other specialty wire bonding requirements.
These gold thickness' are typically 8 +/- 4 micro inches thick.
2. Electroless Nickel Immersion Gold (ENIG)
This is generally done after soldermask and gets applied to exposed
copper areas.
This finish is common and (in the US) is the #2 requested surface
finish.
It costs a bit more than some other finishes like HASL.
3. Normal Gold Finger Plating (usually carried out for PCI cards)
This a electroplated Nickel/ Gold that is a hard gold (alloyed with
Cobalt).
The fabricator generally runs trace/buss bars off the PCB edge to a
common
buss to provide the current during the (post etch) plating process. At
the
edge trim (routing) stage, the trace buss/bar gets cut away along the
gold
plated finger edge.
That covers the gold finishes except that some are available selectively.
Selectively
they generally require additional images/processes and can get rather
pricey.
There's many other finishes too that are not covered here. I agree with Fred
in
discussing these with your supplier. They are aware of what finishes impact
cost.
Cheers,
David Hoover
Sr. Field Application Engineer
Multek - Irvine
----- Original Message -----
From: "Fred Townsend" <fred@xxxxxxxxxxxxx>
To: <AdeelM@xxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, May 21, 2002 6:09 PM
Subject: [SI-LIST] Re: Resistivity of Tin/lead Plating
>
> See below:
>
> Adeel Malik wrote:
>
> > I had to design a bacplane board having many thick power tracks. I
> > calculated the width of the tracks (for a required voltage drop) with
> > respect to 1 oz (or 35 micron) copper weight. But the PCB fab told me
that
> > they woould deposit anadditional 10 micron of copper on the tracks
during
> > electroless copper deposition process. After that another 25 micron of
> > Tin/Lead would be deposited on the copper during tin plating.
> > So the ultimate thickness of copper would be more than I specified. Can
> > someone tell me what value should be substituted for the resisitivity of
> > Tin/Lead to calculate the resistance of the whole track ?.
>
> There is no need to recalculate the resistance. The resistance will
decrease
> very slightly at low frequencies and increase, very slightly at very high
> frequencies. Both effects will be less than your overall tolerance.
>
> >
> >
> > My second question is about the Solder Masks.
> > There are usually 3 types of Solder Mask available from the PCB
> > manufacturers, namely, LPI, Dry Film and Wet. LPI is mostly suited to
track
> > widths in the range of 5-8mils but is less thicker then dry film. Dry
film
> > is more thick but at the same time more expensive. Can someone comment
on
> > the reliability issues of these different Solder Mask types and in which
> > application one should be preferred on another ?.
>
> You do not mention an application that would prefer any one type of mask.
I
> would ask my vendor for their recommendation.
>
> >
> >
> > Lastly, I have a question regarding various surface finishes using Gold.
> > Usually the manufacturers support following types of surface-finish with
> > Gold.
> > 1. Panel Gold Plating (Flash Gold)
> > 2. Electroless Nickel Immersion Gold
> > 3. Normal Gold Finger Plating (usually carried out for PCI cards)
> >
> > Can someone comment on the advantages and disadvantages of these
different
> > types of plating ?.
> >
>
> Again you do not mention your application! Flash (1) is cheapest but can
not
> be used for a contact (too soft). Electroless (2) may work but is not as
> durable as electroplate (3) Au over Ni. Again I would ask my vendor to
> recommend. Trying to save money on gold is usually false economy.
>
>
> Fred Townsend
> DC to Light Consultants
>
> >
> > ADEEL MALIK,
> > Design Engineer,
> > Communications Enabling Technologies,
> > Software Technology Park,
> > 5-A Constitution Avenue,
> > Islamabad, Pakistan.
> > FAX: 92-51-2827469
> > TEL: 92-51-2826160
> >
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