[SI-LIST] Re: PCIX AND Tprop

Brahim,

PCIX timing is measured from a set of standard test loads on the output 
buffers to the receiver input.  These measurments are described in the 
PCIX specification and must be performed using simulation.  If I recall 
correctly, there are two different output test loads used, one for the 
rising edge timing measurement and the other for the falling edge timing 
measurement. Tprop is then the delay from the driver had it been driving 
the test load to the receiver crossing at Vil or Vih the first time for 
minimum specifications and the last time for maximum specifications.

You cannot "just" calculate a maximum trace length without performing 
the simuations with models of the devices on the bus and the board 
traces, along with any coupling to adjacent signal traces that would 
cause additional timing pull-in or push-out.  I would recommend that you 
work with one of the many vary good signal integrity characterization 
tools or with Spice simualtion to come up with the rules that you need 
for your design.  There is no one answer to your question.  It depends 
on the devices connected, the traces on your board, the stackup and 
dielectric properties of the materials, and the spacing of the traces.

Regards,

Scott


-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com


Brahim Koudssi wrote:

>Hello SI Group,
>
>
>Please help me understand the definition of Tprop and how to calculate
>the Max. trace length?
>
>PCIX at fclk=133 mhz
>
>Tprop=2ns
>
>Td= 175ps/in
>
>Thanks,
>
>Brahim Koudssi
>
>
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