[SI-LIST] Re: Decoupling capacitors

  • From: pwelling@xxxxxxxxxxxxxx
  • To: mittalr@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Fri, 17 May 2002 11:01:27 -0600

Hi,

We do not sprinkle 100 pF capacitors on our boards. 

There are times when the vendor recommends that a specific mix of capacitors
(usually along with specific interconnect recommendations) which they it
makes sense, we follow it. This usually happens with very high sample rate
A/D, D/A, DDS, PLLs, etc.

Most of the time, you can obtain well over 100 pF per square inch of high
quality (low inductance) distribute high frequency capacitance if you have
planned your stack-up properly taking advantage of buried plane capacitance.
This has to be managed  with larger BGAs which create areas of plane
perforation (which is not high quality capacitance). Blind, buried, and
micro-vias help with this if cost is not an issue.

I have not been in favor of sprinkling caps. I prefer to place them at the
devices where the energy is required and provide distributed bulk low
frequency capacitance in an area of influence method for the planes.

There may be cases where they may be useful to reduce (damp out) a plane
resonance issue. This would be a layout specific problem though, which would
not occur on many boards.

If I sprinkle anything on boards it would be vias between ground planes to
provide immediate return paths or across the board to provide a more uniform
return path. Another reason for adding additional vias to a design is to
satisfy additional DC current requirements for specific situations.

I would be interested in other oppinions of why someone would want to
sprinkle 100 pF capacitors on a board.

Thanks,

Philip Ross Wellington
Mgr. Signal Integrity & EMI
L-3 Communications CSW


-----Original Message-----
From: mittalr@xxxxxxxxxx [mailto:mittalr@xxxxxxxxxx]
Sent: Friday, May 17, 2002 10:30 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Decoupling capacitors


 
On a slightly tangential topic. Have you ever wondered the need for 100pf
caps. Everyone just seems to sprinkle them as a safety measure but I see no
need for them because
- the IC by itself will have about 50-100pF. I checked with many IC guys and
the ICs where you really need decoupling are generally big enough to have
that much decoupling on-chip. 
- On top of this you have inter-plane caps.

I have seen many of my designs get away with no 100pF caps. I would use 1nF
and 0.1uF, rather than 100pf, 10nF and 0.1uF. Anyone have any other
experience...



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