[SI-LIST] DDR DRAM
- From: "Ravinder Ajmani" <ajmani@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 6 May 2002 16:45:45 -0700
Hi SI Experts,
I am using DDR DRAMs for the first time in our design. The design uses a
single x32 DRAM in point-to-point topology. Due to space constraints, I
have used only source terminations on data bits at the DRAM end. My
simulations show that DRAM drivers are stronger than my ASIC drivers, and I
am able to get reasonable signals in this configuration.
The first version of the card failed to work with DRAM from Manufacturer
"X". We found three data bits failing when they were switching high to
low, and their adjacent bits were switching low to high. We tried DRAM
from Manufacturer "Y" and it seemed to work fine. This card had long DRAM
data lines (about 4" long), so I thought that the board level crosstalk was
an issue. Another card, which had DRAM lines less than 2" also showed same
problem with DRAM "X", but worked fine with DRAM "Y". A further analysis
of ASIC input timings and DRAM output timings show the following:
1) Our ASIC has very little timing margin for the three failing bits.
2) The worst case Data Strobe to Data delay for DRAM "X" varies from 36 ps
to 382 ps for different data bits (measured at the DRAM output), which is
still within DRAM vendor specs. However, at the ASIC end, the same delay
increases to 300 ps to 670 ps for worst case switching.
4) Interestingly, DRAM "Y" appears to be putting Data out BEFORE Data
Strobe, ranging from 100 ps to 400 ps.
Placing parallel termination at ASIC end (680 ohms each to 2.5V and Ground)
seems to help the working of DRAM "X". I have further separated the DRAM
data lines to the extent possible. The length of Data Strobe and Data bits
is matched to within 10% (it is very difficult to improve upon this due to
tight routing space). The simulations on the new card layout show very
little crosstalk (less than 50 mV) with worst case switching.
Our intention is to use both DRAM vendors. While we are working to improve
the ASIC routing (in next revision) to improve timing margin for these
failing bits, I will appreciate your suggestions for making improvements to
board layout.
Regards, Ravinder
PCB Development and Design Department
IBM Corporation
Email: ajmani@xxxxxxxxxx
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