[SI-LIST] Re: DDR DRAM

Chris,

No, your thinking is not sound.  The margins on DDR busses are generally 
low and require careful consideration of in-bus crosstalk.  Crosstalk 
within a bus on the data lines can be looked at in two ways.

#1) Crosstalk can be seen as noise injected from one signal into 
another.  This noise then adds to the instantaneous voltage on the 
victim signal.  This upset can look like additional positive or negative 
overshoot, it can look like IEEE undershoot, in that it it supresses the 
rising edge transition, or it can cause jitter in the waveform.  All of 
these can be detremental on bus operation.  First, jitter translates 
into a reduction of timing margin.  Second, excessive overshoot can 
cause receiver voltage to extend beyond the maximum operating range of 
the device.  This overshoot operation can cause eventual distruction of 
the input through electromigration.

#2) Crosstalk can be seen as a dynamic impedance and propagation 
velocity change on the victim line.  This dynamic change, the magnitude 
is dependent upon the magnitude of the crosstalk, and also commonly 
called the even and odd model coupled transmission line characteristics, 
is another way of looking at why excess jitter, overshoot and IEEE 
undershoot occur in coupled transmission lines.  Again, this can be 
extreme enough to break bus operating margins for both voltage and timing.

Finally, crosstalk from DQ to QDS lines can be catestrophic, since noise 
injected can rise to the extreme of causing false strobe transitions at 
the receivers.  Early DDR chipsets had to be redesigned due to DQ 
signals being routed adjacent to DQS signals inside of packages, causing 
bus failures.

I hope this description helps you.

regards,

scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com

Teraspeed is the registered service mark of 
Teraspeed Consulting Group LLC



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