[SI-LIST] DDR DRAM

I apologize for what might be a simple question...
 

Assuming no other interfaces are in close proximity to a DDR DRAM
databus, is it true that one does not have to worry about crosstalk
between the data bits (or other DRAM signals for that matter)?  Let's
say the traces are only 4 inches long on a PCB.  And assume the case
when a write is occurring.  Since, the controller is not receiving at
the time, is it safe to assume that whatever crosstalk interference
there may be will "settle-out" by the time the DQS strobes the data in?

 

It seems to me that the real worry is only crosstalk from interfaces not
related to the DRAM bus, that could be potentially be switching at the
same time the data is latching into the DRAM.

 

Is this thinking sound?

 

-Chris


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