[SI-LIST] Re: DDR DRAM
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <chris_landrum@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Jul 2004 08:38:37 -0700
Hi Chris,
Actually x-talk control strategy is a critical aspect of the DDR
interface.
There are both SI issues as well as timing issues in designs where
x-talk
is not properly controlled. You really need to use 3 or 4 line fully
coupled
tline models in all simulations, as well as stimulus and aggressor
patterns
that will identify worst case even and odd mode, as well as ISI effects.
The margins nowadays are not that generous, so you really need to=20
develop an efficient strategy. With dual channel platforms it becomes
even more of a challenge. =20
As Scott elluded to, it is usually wise to define your=20
motherboard routing rules so as to provide additional spacing around
clocks and strobes. If you look at a typical Intel design guide we will
often
recommend for example 2H spacing from DQ to DQS, 3H spacing from DQ to
DQS,
and 4H to 5H spacing around clocks. A similar strategy should be adhered
to
in the package. Providing additional spacing around clocks
and strobes is an efficient use of routing space since there are
relatively few
of them. If you limit your xtalk to within the DQ or ADDR bus and keep
your
clocks annd strobes clean you will find much more solution space than if
you simply use a single spacing rule across the interface. =20
Brian P. Moran=20
Senior SIE Engineer=20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Landrum, Chris
Sent: Thursday, July 29, 2004 7:33 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR DRAM
I apologize for what might be a simple question...
=20
Assuming no other interfaces are in close proximity to a DDR DRAM
databus, is it true that one does not have to worry about crosstalk
between the data bits (or other DRAM signals for that matter)? Let's
say the traces are only 4 inches long on a PCB. And assume the case
when a write is occurring. Since, the controller is not receiving at
the time, is it safe to assume that whatever crosstalk interference
there may be will "settle-out" by the time the DQS strobes the data in?
=20
It seems to me that the real worry is only crosstalk from interfaces not
related to the DRAM bus, that could be potentially be switching at the
same time the data is latching into the DRAM.
=20
Is this thinking sound?
=20
-Chris
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=20
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