Posts for si-list, 04-2002

Browse: Last Month: 03-2002 Main Archive Page Next Month: 05-2002

» [SI-LIST] Comment on Radiation from Bends -
» [SI-LIST] -
» [SI-LIST] Complex topology -
» [SI-LIST] Re: Trace Bends -
» [SI-LIST] Re: Trace Bends -
» [SI-LIST] Re: Trace Bends -
» [SI-LIST] Trace Bends -
» [SI-LIST] kapton coaxial cable heating question. -
» [SI-LIST] Eric Bogatin's article on transmission line characteristic impedance -
» [SI-LIST] Re: Clock and data/Address signals simulation -
» [SI-LIST] Re: Clock and data/Address signals simulation -
» [SI-LIST] Looking for a Sr Level SI Engineer -
» [SI-LIST] Eric Bogatin's article -
» [SI-LIST] Clock and data/Address signals simulation -
» [SI-LIST] Ibis model motorola 68040? -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Parametric sweep in Scratch pad -
» [SI-LIST] Re: Clock signal termination -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: Clock signal termination -
» [SI-LIST] Re: Wired-AND VS Wired-OR logic -
» [SI-LIST] [Re: [SI-LIST]: Wired-AND VS Wired-OR logic] -
» [SI-LIST] Re: [SI-LIST]: Wired-AND VS Wired-OR logic -
» [SI-LIST] Re: [SI-LIST]: Wired-AND VS Wired-OR logic -
» [SI-LIST] Re: Clock signal termination -
» [SI-LIST] Re: [SI-LIST]: Wired-AND VS Wired-OR logic -
» [SI-LIST] [SI-LIST]: Wired-AND VS Wired-OR logic -
» [SI-LIST] CAT-5 cable characteristics -
» [SI-LIST] Clock signal termination -
» [SI-LIST] Looking for someone -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] [Asymptotic Waveform Evaluation (AWE)] -
» [SI-LIST] SI software in use or to recommend -
» [SI-LIST] Re: Driving current -
» [SI-LIST] Driving current -
» [SI-LIST] Re: Driving current -
» [SI-LIST] Re: Driving current -
» [SI-LIST] Driving current -
» [SI-LIST] Test for my subscription -
» [SI-LIST] test message. -
» [SI-LIST] Re: Power and ground noise measurement. -
» [SI-LIST] Re: gnd planes connection -
» [SI-LIST] gnd planes connection -
» [SI-LIST] Re: Power and ground noise measurement. -
» [SI-LIST] Power and ground noise measurement. -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: Package options/measurements for substrate noise reduction -
» [SI-LIST] Measuring propagation delay on PWB interconnects -
» [SI-LIST] AW: Re: Run Scheduled Drivers IBIS models on HSPICE 2001.4 -
» [SI-LIST] Looking for someone -
» [SI-LIST] This is a test msg. -
» [SI-LIST] Re: Series Termination Question -
» [SI-LIST] PCB FABRICATION DETAILS -
» [SI-LIST] FW: Re: Series Termination Question -
» [SI-LIST] Re: Series Termination Question -
» [SI-LIST] Package options/measurements for substrate noise reduction -
» [SI-LIST] Re: Series Termination Question -
» [SI-LIST] Series Termination Question -
» [SI-LIST] Re: PCI question -
» [SI-LIST] PCI question -
» [SI-LIST] Re: Run Scheduled Drivers IBIS models on HSPICE 2001.4 -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: Measuring propagation delay on PWB interconnects -
» [SI-LIST] Re: Run Scheduled Drivers IBIS models on HSPICE 2001.4 -
» [SI-LIST] Re: Measuring propagation delay on PWB interconnects -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Run Scheduled Drivers IBIS models on HSPICE 2001.4 -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Test - Delete before reading.... -
» [SI-LIST] Test message - DELETE -
» [SI-LIST] test -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] does changing the edge of board profile help -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] SV: Impedance calcuation -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Re: Impedance calcuation -
» [SI-LIST] Impedance calcuation -
» [SI-LIST] Re: SSO pushout, ground bounce definition -
» [SI-LIST] ROUTING OF A SECOND PCI DEVICE ON AN EXPANSION SLOT -
» [SI-LIST] HSPICE IBIS simulation of MPC948 clock driver has non-monotonic waveform: help please -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Re: Long simulation diverges -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: SSO pushout, ground bounce, IO and core switching -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Re: Terminating a branched clock line -
» [SI-LIST] Long simulation diverges -
» [SI-LIST] Re: Source-Synchronous Interface -
» [SI-LIST] Gil Gafne are you out there? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: ConceptHDL -> BLAST (EDIF) -
» [SI-LIST] Source-Synchronous Interface -
» [SI-LIST] hi -
» [SI-LIST] Re: SSO pushout, ground bounce, IO and core switching -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] Re: WG: Description of Gerber Format Files -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] PCI Buffer Slew Rate -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] WG: Description of Gerber Format Files -
» [SI-LIST] AW: Description of Gerber Format Files -
» [SI-LIST] Description of Gerber Format Files -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] Re: SSO pushout -
» [SI-LIST] SSO pushout -
» [SI-LIST] 0201 Components -
» [SI-LIST] Re: Open Source Waveform Viewer for HSPICE -
» [SI-LIST] Open Source Waveform Viewer for HSPICE -
» [SI-LIST] PCI Buffer Slew Rate -
» [SI-LIST] Re: Max operating temps. -
» [SI-LIST] Max operating temps. -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] Re: what is the conductivity of a dielectric? -
» [SI-LIST] what is the conductivity of a dielectric? -
» [SI-LIST] Re: Minimum Tracelength -
» [SI-LIST] Minimum Tracelength -
» [SI-LIST] Impedance of microstrip with/without GND plane -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: HSPICE TR0 error -
» [SI-LIST] HSPICE TR0 error -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Signal Integrity/High speed design course in India -
» [SI-LIST] Re: Allegro ? -
» [SI-LIST] Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: Spice models encryption -
» [SI-LIST] Spice models encryption -
» [SI-LIST] High Data Rate Cables (II) -
» [SI-LIST] Re: Signal Integrity/High speed design course in India -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Signal Integrity/High speed design course in India -
» [SI-LIST] Signal Integrity/High speed design course in India -
» [SI-LIST] Re: Allegro ? -
» [SI-LIST] Re: Allegro ? -
» [SI-LIST] Re: Allegro ? -
» [SI-LIST] Re: Allegro ? -
» [SI-LIST] Allegro ? -
» [SI-LIST] Re: Connector simulation model -
» [SI-LIST] Re: Connector simulation model -
» [SI-LIST] SV: Connector simulation model -
» [SI-LIST] Re: Connector simulation model -
» [SI-LIST] Crosstalk on coupled striplines -
» [SI-LIST] Connector simulation model -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: High Data Rate Cables -
» [SI-LIST] High Data Rate Cables -
» [SI-LIST] Re: rGMII simulation model -
» [SI-LIST] Re: ConceptHDL -> BLAST (EDIF) -
» [SI-LIST] Re: backplane connector -
» [SI-LIST] Re: rGMII simulation model -
» [SI-LIST] PCI V2.2 output drive and slew rate question -
» [SI-LIST] rGMII simulation model -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Printed wiring board to chassis coupling -
» [SI-LIST] SpeccraQuest ESPICE Resistor pack delay -
» [SI-LIST] Interactive IFS-PRO -
» [SI-LIST] Re: AW: Re: PCB via simulations -
» [SI-LIST] AW: S-parameter to SPICE -
» [SI-LIST] -ve Setup Time and Hold time. -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Re: Off Track system question -
» [SI-LIST] Off Track system question -
» [SI-LIST] Delay between signal and trigger -
» [SI-LIST] AW: Re: PCB via simulations -
» [SI-LIST] Re: PCB via simulations -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] AW: Re: PCB via simulations -
» [SI-LIST] Re: PCB via simulations -
» [SI-LIST] PCB via simulations -