Hi Everyone, I just got back from Easter break and read through this thread. I thought it worth mentioning that IBIS 4.0 will bring us a new mechanism for insuring the quality of IBIS model data: Golden Waveforms. The new syntax lets us include HSPICE or lab waveforms for an "arbitrary load" directly in the IBIS code. In theory, this means you can check the validity of the model data AND the ability of the simulator to replicate the original waveforms whenever you fire up a simulation. This is cool. If you want to read more about it, check out BIRD 70 on the IBIS web page. Ascend soapbox: please think about including Golden Waveforms as a requirement on your upcoming component purchase specs. Greg Edlund Advisory Engineer Electronic Packaging Integration IBM Server Technology Development 3605 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@xxxxxxxxxx From: Todd Westerhoff [mailto:twester@xxxxxxxxxxx] Sent: Tuesday, March 26, 2002 11:55 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: IBIS Model Quality (or lack thereof) Thanks everyone, for your contributions to this thread so far. By way of summary, we've heard from the following semiconductor companies: - Intel - Fairchild - Serverworks (if I left anyone out, my apologies) ... and I'll vouch for both Intel and Micron myself, both in terms of model quality and support. It is my strong suspicion that precious few IBIS models are validated in any meaningful way before they are shipped to the customer. A few of your have expressed hopes for the IBIS model quality committee that has just gotten started, I share your hopes and enthusiasm for the effort. A number of you have outlined some of the testing processes you use, and I'd like to suggest that we explore that subject a bit more. We've spent a LOT of time here lately correlating IBIS models to their HSpice counterparts. We're currently using two "standard" text fixtures to compare IBIS/HSpice models: * I/O buffer connected to VDDQ/2 through 50 ohms * I/O buffer connected to 0.5ns, 50ohm tline, 5pf to GND at tline end The theory is that the first test fixture compares rising/falling edge characteristics and buffer strength, while the second test models the driver's response to a reflected wave (primarily the value of C_Comp). If you get the HSpice/IBIS buffers to agree across these two tests, chances are the rest of the puzzle falls into place, provided you agree on things like pin parasitics and switching thresholds. So, I'm curious - for those of you who test IBIS models against any kind of reference (HSpice or measurement) - what kinds of test loads are you using, and what are you looking for? As always, all input (on and off the list) is greatly appreciated. Todd. Todd Westerhoff Signal Integrity Engineer Hammerhead Networks 5 Federal Street - Billerica, MA - 01821 email:twester@xxxxxxxxxxx - ph: 978-671-5084 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu