[SI-LIST] [Re: [SI-LIST]: Wired-AND VS Wired-OR logic]

Here is my thinking:

If the connected gates are active low, then the low voltage on the line
is
interpreted as a logic
one.  Thus L(low voltage)=1 and H(High voltage)=0.
Which makes sense since a NMOS device will turn on a low voltage at its
gate.

With this in mind, for two open drain drivers, as long as one of the
drivers is ON
then voltage on the
line will be low i.e., the logic driven will be 1.  Thus

Driver A    Driver B      Line Voltage       Logic

OFF(0)     OFF(0)            H                0
 *          ON(1)            L                1
ON(1)        *               L                1




Which to me looks like the truth table of an OR gate.   Read as:

"Either A or B is on, the output is Logic High".

Abhijit.












Anand.Kuriakose@xxxxxxxxxx wrote:

> Hi all,
>
> We can introduce wired-AND logic by connecting 2 or more open-drain (also
> open-collector) outputs together with a single pull-up resister. The logic of
> AND logic results as follows: If one or more of the drivers asserts the output
> to low state (electrically low ), the equivalent output is low, which is how 
> an
> AND gate functions. Also the connected signals have to be active-low signals.
>
> I have seen many documents refering to the above scenario as wired-OR logic. 
> It
> doesnt make sense. Also the PCI spec 2.2, sec2.1 refers to O/D signals (ex 
> INTX#
> and SERR#) as to be capable of introducing wired-OR logic.
>
> So what is wired-OR logic? How do we realise this logic? Does the active level
> of the connected signals make the difference?
>
> Also one more question.  When it comes to wired-AND logic, only one device can
> assert its output low. We cannot have more than one device asserting its 
> output
> low simultaneously. Am i right in saying so. If yes, is this allowed in 
> wired-OR
> logic.
>
> Thanx in advance for all the valuable inputs.
>
> Regards,
> Anand Kuriakose.
>
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