[SI-LIST] Re: SSO pushout, ground bounce, IO and core switching

Raymond,
Thanks for the link to the doc. I read
"http://www.sigrity.com/papers/ECTC2001/ECTC_LI1.pdf";.
In there, the authors show the effect of on-die decoupling on SSO power/gnd
noise. The tables and conclusion say
on-die decoupling cap can reduce power/ground noise. I can see how it
reduces the power line noise.
However, I can not understand how the on-die decoupling cap which is placed
between power and
gound (on die, vss or substrait) can reduce the gound bounce. None of the
waveforms in this paper shows
the ground line. Can you please comment on that? Thanks.
Regards,
Kevin Hui
LSI Logic


----- Original Message -----
From: "Raymond Y. Chen" <chen@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Cc: <linwee70@xxxxxxxxx>; <Andrew.Ingraham@xxxxxxxxxx>
Sent: Thursday, April 11, 2002 2:57 PM
Subject: [SI-LIST] Re: SSO pushout, ground bounce, IO and core switching


>
> During Simultaneous Switching Output (SSO) stage of I/O buffers, the basic
> Electromagnetic (EM) phenomena affect the timing and waveform of the
> signals. Trace coupling (even/odd mode for example) affect timing and
> waveform during SSO. Power/Ground bounce (also referred as Simultaneous
> Switching Noise - SSN) is another major mechanism that affects Signal
> Integrity, since power/gound is the signal return path. Any voltage
> fluctuations on the power/gound affect the driver switching
characteristics,
> driver/receiver end waveforms, and signal waveforms along the path where
> power/gound noise can reach in the form of EM wave propagation. You can
> think as moving charge, flux, inductance, and displacement current as
well.
> In essence, Maxwell equations rule.
>
> To illustrate this point and to see the mechanism that contribute to "SSO
> Pushout", I just put up an animated slides on our web site to show the
> relation between SSO, power/gound bounce, signal Return Path Discontinuity
> (RPD), and signal timing and waveform degradation.
> http://www.sigrity.com/papers/reply20020411/speedxp_ssn.ppt
>
> And also here is a functional demo software to simulate this topic.
> http://www.sigrity.com/prod01_demodl.htm
> An application example is included (application notes, example 7) to see
the
> SSO of 17 nets with gound bounce and RPD, with and without decoupling
> capacitors. You can change many parameters, such as with/without trace
> coupling, edge rates, power/ground structures, various decoupling
capacitors
> (models and locations), different switching bit patterns, even/odd mode. A
> good technical paper to reference on this kind SSO simulation is "A
> Simulation Study of Simultaneous Switching Noise" at:
> http://www.sigrity.com/papers/ECTC2001/ECTC_LI1.pdf
>
> In the case of core logic SSO, the strong power/gound transient currents
> will generate dynamic EM noise and couple into I/O. This phenomenon is
> pointed out on another thread these two days - by Gil Gafni on topic of
> "PCI Buffer Slew Rate", and you can also refer to this paper "Integrated
> Modeling Methodology for Core and I/O Power Delivery" for some
discussions:
> http://www.sigrity.com/papers/ECTC2001/ECTC_LI2.pdf
>
> Finally I want to point out, just as Andy said, SSO noise phenomena could
> either increase or reduce the signal delay. You can try to build an
example
> with the demo software to show this, even though this time I only provided
> the slides for "SSO Pushout".
>
> Raymond Y. Chen
> Vice President, Products and Services
> Sigrity, Inc.
> ********************************************
> 4675 Stevens Creek Blvd. Suite 130
> Santa Clara, CA 95051
> 408.260.9344 Ext 102
> ********************************************
> www.sigrity.com
>
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ingraham, Andrew
> > Sent: Thursday, April 11, 2002 6:34 AM
> > To: linwee70@xxxxxxxxx
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SSO pushout
> >
> >
> > > " SSO pushout is a result of multiple drivers
> > > switching simultaneously. It impacts signal integrity
> > > through adding extra delay to the propagating signal"
> > >
> > > I understand that we'll have more current in the
> > > return path due to simultaneous switching that may
> > > cause ground/plane bounce, but couldn't relate that to
> > > delay.
> > >
> > > Can someone explain this  delay, as the text doesn't
> > > explain that ?
> >
> > There are a few mechanisms that result in extra delay.  (It isn't
> > really a delay in the propagating signal, i.e. wires, but rather in
> > the driven signal coming out of the IC outputs.)
> >
> > One of them is simply this.  When several outputs switch from high to
> > low, switching current flows in through the signal pins and N times
> > as much current goes out through the "ground" pins.
> >
> > The ground system impedance turns this current into ground bounce,
> > where on-die "ground" momentarily lifts above board "ground".
> >
> > For the outputs switching low, the pull-down transistor is on, so
> > this ground bounce gets added to their outputs.  Imagine simply
> > adding a small positive pulse to the outputs, while they switch.
> > Their falling edges are lifted up slightly, which also has the
> > appearance of moving them a little to the right --> greater delay.
> >
> > So it is really just crosstalk by way of the on-die ground bounce.
> >
> > The same thing happens for rising edges, except it is the VDD or VCC
> > that bounces or sags.
> >
> > I'm sure there are other mechanisms at work too.  Note that SSO
> > can both increase and decrease delays, at least in principle.
> >
> > Regards,
> > Andy
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Gil Gafni
> > Sent: Wednesday, April 10, 2002 12:21 PM
> > To: Si-List
> > Subject: [SI-LIST] PCI Buffer Slew Rate
> >
> >
> > Hello Experts,
> >
> > As part of an SSO analysis that we are conducting, we noticed an odd
> > behavior of the PCI buffer -
> > 1. It looks like it is influenced by the noise on the core Vdd
> > (logic side of it) and NOT to the IO Vdd.
> > 2. The sensitivity to Vdd core changes is very high; any added
> > 100mV of noise can add 1nSec to the pushout.
> >
> > The bottom line is that with a moderate noise on Vdd of 375 mV we have
> > 1nS of push out, and find it very hard to pass (no or negative margins)
> > Any recommendations?
> >
> > Regards,
> >
> > Gil Gafni
> >
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>
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