Posts for si-list, 03-2002

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» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: ISF2XTK error-Urgent-Urgent -
» [SI-LIST] ISF2XTK error-Urgent-Urgent -
» [SI-LIST] Re: ATA 100 bus simulation -
» [SI-LIST] ATA 100 bus simulation -
» [SI-LIST] test -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: IBIS MODEL QUESTION -
» [SI-LIST] Re: Nagel's Thesis -
» [SI-LIST] Re: RDRAM termination -
» [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: Stitching Capacitors, Split-planes & Return Currents ? -
» [SI-LIST] Re: RDRAM termination -
» [SI-LIST] What should be checked on ASIC -
» [SI-LIST] Re: RDRAM termination -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Nagel's Thesis -
» [SI-LIST] Re: Stitching Capacitors, Split-planes & Return Currents ? -
» [SI-LIST] IBIS Model of the CMOS PECL ????? -
» [SI-LIST] IBIS Model of the CMOS PECL ????? -
» [SI-LIST] IBIS Model of the CMOS PECL ????? -
» [SI-LIST] IBIS Model of the CMOS PECL ????? -
» [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] IBIS Model of the CMOS PECL ????? -
» [SI-LIST] RDRAM termination -
» [SI-LIST] IBIS MODEL QUESTION -
» [SI-LIST] Stitching Capacitors, Split-planes & Return Currents ? -
» [SI-LIST] Re: backplane connector -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: backplane connector -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: TDR's and ESD Protection -
» Re: [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Message submitted to 'si-list' -
» [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: S-parameter to SPICE -
» [SI-LIST] backplane connector -
» [SI-LIST] S-parameter to SPICE -
» [SI-LIST] Re: XTK error -
» [SI-LIST] Re: Question on split termination -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Why does lamination fail to prevent eddy currents at high frequencies? -
» [SI-LIST] Re: XTK error -
» [SI-LIST] XTK error -
» [SI-LIST] Re: High Speed Digital design education? -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: Frequency spectrum of SONET data -
» [SI-LIST] High Speed Digital design education? -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: TDR's and ESD Protection -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: Frequency spectrum of SONET data -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Frequency spectrum of SONET data -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: Interpretation of XTK results -
» [SI-LIST] Re: logic analyzer probes on LVDS -
» [SI-LIST] TDR's and ESD Protection -
» [SI-LIST] Interpretation of XTK results -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: Looking for Teradyne SI contact information....... -
» [SI-LIST] Re: Looking for Teradyne SI contact information....... -
» [SI-LIST] Looking for Teradyne SI contact information....... -
» [SI-LIST] Re: logic analyzer probes on LVDS -
» [SI-LIST] Fwd: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] logic analyzer probes on LVDS -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof)- Cleansing service -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] Re: IBIS Model Quality (or lack thereof) -
» [SI-LIST] IBIS Model Quality (or lack thereof) -
» [SI-LIST] inter-power-converter coupling -
» [SI-LIST] Re: Turn on oscillation power analysis -
» [SI-LIST] Job opening -
» [SI-LIST] simulation in SCRATCHPAD -
» [SI-LIST] Re: ISI simulation in SCRATCHPAD (XTK) -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] ISI simulation in SCRATCHPAD (XTK) -
» [SI-LIST] Re: Turn on oscillation power analysis -
» [SI-LIST] Re: Turn on oscillation power analysis -
» [SI-LIST] ASIC PKG for PCI-X -
» [SI-LIST] see the attached PDF-File - SI tool for a particular layer stackup -
» [SI-LIST] SI tool for a particular layer stackup -
» [SI-LIST] Re: Few analog power supplies, where to short it. -
» [SI-LIST] Few analog power supplies, where to short it. -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Connector for LVDS -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Series termination value -
» [SI-LIST] Connector for LVDS -
» [SI-LIST] Re: Connector for LVDS -
» [SI-LIST] Re: Connector for LVDS -
» [SI-LIST] Re: Connector for LVDS -
» [SI-LIST] Connector for LVDS -
» [SI-LIST] Series termination value -
» [SI-LIST] Determining Edge rate -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Power Supply Layout -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Re: Need for SI Service Bureaus? -
» [SI-LIST] Need for SI Service Bureaus? -
» [SI-LIST] Re: Fourier Series, trapeziod Found it!! -
» [SI-LIST] Re: Fourier Series, trapeziod -
» [SI-LIST] Re: Fourier Series, trapeziod -
» [SI-LIST] Re: Non monotonic EDGE on Clocks -
» [SI-LIST] Re: Decoupling Capacitors -
» [SI-LIST] Re: Fourier Series, trapeziod -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Specctraquest Model ? -
» [SI-LIST] Re: Non monotonic EDGE on Clocks -
» [SI-LIST] Non monotonic EDGE on Clocks -
» [SI-LIST] Re: Fourier Series, trapeziod -
» [SI-LIST] unsubsribe -
» [SI-LIST] Re: re -
» [SI-LIST] Re: Specctraquest Model ? -
» [SI-LIST] Re: Decoupling Capacitors -
» [SI-LIST] Re: Embedded Passives -
» [SI-LIST] Fourier Series, trapeziod -
» [SI-LIST] Re: Specctraquest Model ? -
» [SI-LIST] Specctraquest Model ? -
» [SI-LIST] PECL to ECL at 1GHz+ -
» [SI-LIST] Decoupling Capacitors -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] FWD: Re: Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Signal Integrity Venues -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] Re: SQ Question. -
» [SI-LIST] SQ Question. -
» [SI-LIST] SSO Analysis -
» [SI-LIST] microstrip and stripline FREE-FEM examples -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: Generating PRBS -
» [SI-LIST] Re: Generating PRBS -
» [SI-LIST] Re: Generating PRBS -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Generating PRBS -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SpectraQuest Question. -
» [SI-LIST] SSO Analysis -
» [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] SPECCTRAQuest: DC level shift with series caps -
» [SI-LIST] Re: SpectraQuest Question. -
» [SI-LIST] SpectraQuest Question. -
» [SI-LIST] Re: trace configuration ?? -
» [SI-LIST] EMI Test Lab -
» [SI-LIST] Help On High Speed Interconnections -
» [SI-LIST] Looking for someone I can bounce some ansoft questions off of off line..... -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] trace configuration ?? -
» [SI-LIST] 576MHz board design... again -
» [SI-LIST] clearance -
» [SI-LIST] Crosstalk -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] 576MHz board design -
» [SI-LIST] Model File -
» [SI-LIST] Re: (no subject) -
» (no subject) -
» [SI-LIST] Loss requirements in Infiniband spec. (si-list Digest V2 #70) -
» [SI-LIST] SSTL2 characterisation -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] capacitive coupling to cables -
» [SI-LIST] Loss requirements in Infiniband spec... -
» [SI-LIST] Re: C_comp in IBIS -
» [SI-LIST] Re: Hspice encryption -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] Re: Using S-parameter files in HSPICE -
» [SI-LIST] Re: Series MOSFET IBIS models in SigXplorer -
» [SI-LIST] Re: Series MOSFET IBIS models in SigXplorer -
» [SI-LIST] Re: Has any one taken the Todd Hubing UMR video course on EMC..... -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] Re: Spiral inductor L and Q measurement with VNA -
» [SI-LIST] Series MOSFET IBIS models in SigXplorer -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] Re: Spiral inductor L and Q measurement with VNA -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Spiral inductor L and Q measurement with VNA -
» [SI-LIST] Re: XTK analysis-help -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] help , about boardside coupling impendence calc -
» [SI-LIST] XTK analysis-help -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] AC coupling capacitors -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] C_comp in IBIS -
» [SI-LIST] Specifying Clock to Out delay in IBIS Files -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] Re: lee richey course etc -
» [SI-LIST] lee richey course etc -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] X2Y 'zero' inductance caps -
» [SI-LIST] Even mode and common mode- SI and EMC worlds -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] help -
» [SI-LIST] SI for a LVDS system -
» [SI-LIST] Re: VIA L and C values. -
» [SI-LIST] VIA L and C values. -
» [SI-LIST] SiQual Design Con Papers Posted -
» [SI-LIST] Has any one taken the Todd Hubing UMR video course on EMC..... -
» [SI-LIST] Start-up opening -
» [SI-LIST] Re: Even mode and common mode -
» [SI-LIST] OUtput impedance measurement -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Even mode and common mode -
» [SI-LIST] Re: FREE-FEM -
» [SI-LIST] Re: FFT/iFFT tool (for FREE) -
» [SI-LIST] Re: Even mode and common mode -
» [SI-LIST] Re: Even mode and common mode -
» [SI-LIST] Even mode and common mode -
» [SI-LIST] Re: FREE-FEM -
» [SI-LIST] Re: Split planes -
» [SI-LIST] Re: E-M SOLVERS - HOW DO THEY WORK? -
» [SI-LIST] Split planes -
» [SI-LIST] Re: Inverting PWL Current sources in HPSice -
» [SI-LIST] E-M SOLVERS - HOW DO THEY WORK? -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Inverting PWL Current sources in HPSice -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] LVDS output impedance and teminations -
» [SI-LIST] Re: FREE-FEM -
» [SI-LIST] Re: Inductance of Various Capacitor Paxkages -
» [SI-LIST] Re: FFT/iFFT tool (for FREE) -
» [SI-LIST] FFT/iFFT tool (for FREE) -
» [SI-LIST] Re: FREE-FEM -
» [SI-LIST] GMII timings -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] Re: Importance of Package Height -
» [SI-LIST] FREE-FEM -
» [SI-LIST] Re: Inductance of Various Capacitor Paxkages -
» [SI-LIST] Re: Optimal Power/ground lauout for a 2-layer PCB -
» [SI-LIST] Re: LC values for IBIS generation: mutual, self, or both? -
» [SI-LIST] Re: High Speed Serial Links Using LV Differential Receivers -
» [SI-LIST] Signal Integrity Engineer position open at Chelsio Communications -
» [SI-LIST] Re: High Speed Serial Links Using LV Differential Receivers -
» [SI-LIST] Re: Spice model for power subsystem. -
» [SI-LIST] Re: Even mode, common mode, and mode conversion -
» [SI-LIST] Re: Spice model for power subsystem. -
» [SI-LIST] Re: Even mode, common mode, and mode conversion -
» [SI-LIST] Importance of Package Height -
» [SI-LIST] Re: Effect of USB attachment's current drawn through motherboard bypass network -
» [SI-LIST] High Speed Serial Links Using LV Differential Receivers -
» [SI-LIST] How does temperature and voltage change effect the output signal of the chip ? -
» [SI-LIST] Spice model for power subsystem. -