[SI-LIST] Re: Clock and data/Address signals simulation

Hi Joe:

One reason that you may find different opinions on this is that different
people have different tolerances for risk.  If simulation shows that a
signal oscillates around Vil or Vih, you may or may not see false clocking
on an actual board, depending on a number of factors.  For one thing, these
values--from the IC manufacturer--should be fairly conservative (ideally),
indicating the point at which you might see a glitch.

I can't agree, though, if someone recommended that you ignore this type of
problem when it shows up in a simulation.  Just because it doesn't bite you
in one case, doesn't make it a good engineering practice to ignore the
possibity that it might bite you in a different manufacturing run, or on a
different design.

You asked, earlier, whether anyone was doing seminars in India.  I have been
discussing the possibility of Cognition doing some seminars in India this
summer.  If you're still interested (or anyone else in India, for that
matter), e-mail me your contact info, and I'll forward it to my associate in
Bangalore).

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com


> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Joe Young
> Sent: Friday, April 26, 2002 12:04 PM
> To: si-list@xxxxxxxxxxxxx; ldsmith@xxxxxxxxxxxxxxxxxx
> Subject: [SI-LIST] Clock and data/Address signals simulation
>
>
>
> Hi Gurus,
>        How do u decide whether a clock/data signal is good/or in
> acceptable range while doing simulation especially when it is
> having threshold multi crossing error. I found different persons
> are having different opinions.
>       I would like to hear your opinions also...your one penny
> suggestion may improve 0.1 penny of my knowledge :)
>
>
> rgds,
> Joe
> --
>
> On Tue, 16 Apr 2002 13:55:44
>  Larry Smith wrote:
> >
> >Hmmm.  Looks like my table separated by tabs did not make it...
> >I'll try it again.  The table in the text has been replaced.
> >
> >------------- Begin Forwarded Message -------------
> >
> >Ege - I don't believe there is any contridiction between non-unique
> >inductance matricies and unique system voltages.  Partial inductances
> >are valid as long as they are defined in the context of a loop.
> >Partial inductances by themselves have no meaning.  But in an
> >inductance matrix, where they are combined with all partials and
> >mutuals in a loop, the extracted values (not unique) can be used to
> >find unique voltages and currents within that loop.
> >
> >Take the example of two connector pins, one used for a signal and the
> >other used for ground.  Loop inductance in this case is L1+L2-2*M12
> >(the sum of the self inductances minus two times the mutual inductance
> >between them).  The following partial and mutual inductances might be
> >obtained from two different electromagnetic extractors:
> >
> >extractor   L1      L2      M12     Loop L   units
> >---------   -----   -----   -----   ------   -----
> >1           10      10      9        2       nH
> >2           2       2       1        2       nH
> >
> >Which extractor got the right answer?  They both did.  Partial and
> >mutual inductances are meaningless outside the context of a loop.  Both
> >sets of extracted data give the same loop inductances and will lead to
> >unique voltages and currents when the loop is simulated in a circuit
> >analysis tool, even though the extracted partial and mutual inductances
> >are not unique. =20
> >
> >I see a lot of engineers try to use partial inductance (alone) in a
> >circuit simulation.  This is at best misleading and may give flat out
> >wrong answers in the simulation.  I don't think you will find any
> >disagreement between Al Ruehli, Bryan Young or any of the other experts
> >in this matter (please comment if I have misspoken).
> >
> >Now concerning measurements, simulation, SI and EMI...  For SI
> >purposes, it only makes sense to measure voltages in very local areas
> >with a probe that has a very short ground lead.  When we measure a
> >signal with respect to (WRT) local ground, we have measured a
> >"difference" voltage.  This is a differential measurement, even if it
> >is done with a single ended probe.  We have not measured the signal WRT
> >spice node 0, the center of the earth, or any other place in the
> >system.  If a simulation is set up correctly, the inductance matrix
> >from either extractor 1 or 2 above will deliver an inductance matrix
> >that can be simulated and match the hardware measurement of a signal
> >WRT it's local ground.
> >
> >As Raymond Chen has stated in points one and two below, it does not
> >make sense to measure anything other voltage WRT local ground.  There
> >are at least two problems with measurements that are not made WRT local
> >ground.  If we try to measure across several inches (significant
> >portion of a wavelength) we are trying to measure across a time delay.
> >What meaning is there in voltage measured across time?  If we try to
> >measure across a big inductance (i.e. connector pin), magnetic flux
> >will penetrate the loop involving the inductance, probe and ground
> >lead.  The size of the measurement loop will determine the magnetic
> >flux "captured" by that loop and lead to non unique measurements which
> >depend on where the ground lead is positioned WRT the inductance.  With
> >probes, the only legitimate thing to measure is the difference between
> >a node and it's local reference point, hopefully in an area where the
> >time varying magnetic field is not significant.
> >
> >Even though we don't have a good way to measure "ground bounce" across
> >a connector, I believe a circuit simulator with the inductance matrix
> >from either extractor 1 or 2 above is capable of simulating the correct
> >voltage across the ground pin of a connector (and getting an identical
> >voltage solution from either matrix).  If 10 signals crossed the
> >connector and all switched the same way at the same time, there would
> >be a huge (almost Vdd) voltage across the single ground pin.  This is
> >real and is what we call the SSN or SSO problem.  It can cause flipped
> >bits and EMI radiation as one local ground gets perturbed WRT to the
> >other.  Simulations of "ground bounce" are probably more trustworthy
> >than measurement, assuming that all partial inductances and mutual
> >inductances are given in the context of a loop.  It is difficult to
> >measure ground bounce directly.  The best indicators of ground bounce
> >are funny waveforms at the far end of a quiet line and EMI radiation.
> >
> >regards,
> >Larry Smith
> >Sun Microsystems
> >
> >
> >> From: Ege Engin <engin@xxxxxxxxxx>
> >>=20
> >> Raymond,
> >>=20
> >> The first thing that comes up to my mind is the concept of
> partial induct=
> >ance. Some
> >> experts work with a unique defined partial inductance (e.g.,
> C.R.Paul, A.=
> >E.Ruehli),
> >> whereas some are against such a unique definition (e.g.,
> B.Young). I supp=
> >ose you
> >> fall into the second category. Indeed SI issues can be
> investigated using=
> > solely
> >> terminal voltages (your 2.point). But voltage drop *along the
> conductor i=
> >tself* can
> >> also give valuable information regarding the EMI behavior,
> because it can=
> > model some
> >> unintended dipole antennas (according to the experts falling
> into the fir=
> >st
> >> category). The question is, how can one resolve this
> contradiction, that =
> >an
> >> ill-defined voltage in terms of SI becomes a useful tool in
> terms of EMI?
> >>=20
> >> Regards
> >> Ege
> >>=20
> >> "Raymond Y. Chen" schrieb:
> >>=20
> >> > Kevin,
> >> >
> >> > You raised a good question, and I=92ve been asked many times
> on this is=
> >sue, so
> >> > please see my comments after your post:
> >> >
> >> > > Raymond,
> >> > > Thanks for the link to the doc. I read
> >> > > "http://www.sigrity.com/papers/ECTC2001/ECTC_LI1.pdf";.
> >> > > In there, the authors show the effect of on-die decoupling on SSO
> >> > > power/gnd
> >> > > noise. The tables and conclusion say
> >> > > on-die decoupling cap can reduce power/ground noise. I can
> see how it
> >> > > reduces the power line noise.
> >> > > However, I can not understand how the on-die decoupling cap which
> >> > > is placed
> >> > > between power and
> >> > > gound (on die, vss or substrait) can reduce the gound
> bounce. None of=
> > the
> >> > > waveforms in this paper shows
> >> > > the ground line. Can you please comment on that? Thanks.
> >> > > Regards,
> >> > > Kevin Hui
> >> > > LSI Logic
> >> >
> >> > First of all, voltage is defined between 2 nodes. So power
> bounce is no=
> >t
> >> > something happening on power rail alone, it is the voltage
> fluctuation
> >> > between power and ground.
> >> >
> >> > So where is the ground bounce voltage? It must be defined
> between 2 nod=
> >es.
> >> > And usually people will show such circuit diagram to define
> ground boun=
> >ce (I
> >> > borrowed the drawing from ADEEL AHMAD=92s 4/10 post on this topic):
> >> >
> >> >                         -------PAD
> >> >                         |
> >> >                         |
> >> >                       NMOS
> >> >                         |
> >> >                         |<<internal GND
> >> >                      INDUCTOR
> >> >                         |
> >> >                     GROUND PIN
> >> >
> >> > Here the ground bounce is defined as the voltage drop
> crossed the induc=
> >tor,
> >> > which models the interconnect parasitics (ground via, trace, plane)
> >> >
> >> > However, this definition derived from circuit-theory point
> of view ofte=
> >n is
> >> > not valid and causes misleading concepts, especially in the
> high-speed
> >> > design arena where Electromagnetic (EM) phenomena is the
> basics for all
> >> > circuit or SI issues. Because:
> >> >
> >> > 1.      measuring voltage across a big distance (compare to
> wavelength)=
> > is not
> >> > well defined. For example, defining the voltage between
> die-pad and the
> >> > package-pin; or defining the voltage between a point in the
> middle of a=
> > PCB
> >> > and a point at the edge of the PCB, are not good if you are
> working in =
> >the
> >> > hundreds of MHz range and beyond.
> >> > 2.      measuring AC voltage drop along the conductor itself
> is not def=
> >ined. For
> >> > example, we often measure the voltage at the ends of a
> transmission lin=
> >e
> >> > (the 2 ports); we don=92t measure the voltage drop across
> the individua=
> >l
> >> > transmission line conductor. Voltage drop along the ground
> conductor (e=
> >xcept
> >> > DC) is not well defined based on EM theory. Think about
> this, in the ab=
> >ove
> >> > drawing, the inductor can not associate with just the conductor, the
> >> > inductor has to associate with a loop, where is the loop?
> >> >
> >> > After all, the terminology of ground bounce itself can be misleading,
> >> > because lot of people think that ground bounce can be viewed
> ON the gro=
> >und
> >> > conductor, whereas actually ground bounce happens BETWEEN
> power and gro=
> >und.
> >> > The only time you may and you can well define the voltage
> between 2 gro=
> >und
> >> > points is if these 2 ground points are very close (local
> port). For exa=
> >mple,
> >> > between 2 ground C4 bumps. At that time, most flux in this
> loop is well
> >> > captured between these 2 points.
> >> >
> >> > Therefore it may be better to use the term Power/ground
> fluctuation ins=
> >tead
> >> > of ground bounce.
> >> >
> >> > Lastly, please take a look at the commonly used
> one-dimension power del=
> >ivery
> >> > model (illustrative):
> >> >
> >> >           L     R         L     R         L     R         1
> >> >      |---ooo---^^^---|---ooo---^^^---|---ooo---^^^---|----|
> >> >      |               |               |               |    |
> >> > VRM ___              |               |               |    |
> >> >      -               |               |               |    |
> >> >      |        decap =3D=3D=3D       decap =3D=3D=3D
> Cdie =3D=3D=
> >=3D  |> buffer
> >> >      |               |               |               |    |
> >> >      |     PCB       |    Pkg        |    chip       |    |
> >> >      |               |               |               |    |
> >> >      |---ooo---^^^---|---ooo---^^^---|---ooo---^^^---|----|
> >> >      2                                                    0
> >> >
> >> > To a driver, what is important is the local supply voltage
> between node=
> > 1
> >> > and 0 (power and ground). And only V(1,0) can be well
> defined in the co=
> >rrect
> >> > EM sense. The so-called =93ground bounce=94 between node 2
> and 0 will b=
> >e ill
> >> > defined and meaningless to the driver.
> >> >
> >> > Regards,
> >> >
> >> > Raymond Y. Chen
> >> > Sigrity, Inc.
> >> >
> >> > > ----- Original Message -----
> >> > > From: "Raymond Y. Chen" <chen@xxxxxxxxxxx>
> >> > > To: <si-list@xxxxxxxxxxxxx>
> >> > > Cc: <linwee70@xxxxxxxxx>; <Andrew.Ingraham@xxxxxxxxxx>
> >> > > Sent: Thursday, April 11, 2002 2:57 PM
> >> > > Subject: [SI-LIST] Re: SSO pushout, ground bounce, IO and
> core switch=
> >ing
> >> > >
> >> > >
> >> > > >
> >> > > > During Simultaneous Switching Output (SSO) stage of I/O
> >> > > buffers, the basic
> >> > > > Electromagnetic (EM) phenomena affect the timing and
> waveform of th=
> >e
> >> > > > signals. Trace coupling (even/odd mode for example)
> affect timing a=
> >nd
> >> > > > waveform during SSO. Power/Ground bounce (also referred
> as Simultan=
> >eous
> >> > > > Switching Noise - SSN) is another major mechanism that
> affects Sign=
> >al
> >> > > > Integrity, since power/gound is the signal return path.
> Any voltage
> >> > > > fluctuations on the power/gound affect the driver switching
> >> > > characteristics,
> >> > > > driver/receiver end waveforms, and signal waveforms
> along the path =
> >where
> >> > > > power/gound noise can reach in the form of EM wave
> propagation. You=
> > can
> >> > > > think as moving charge, flux, inductance, and
> displacement current =
> >as
> >> > > well.
> >> > > > In essence, Maxwell equations rule.
> >> > > >
> >> > > > To illustrate this point and to see the mechanism that
> >> > > contribute to "SSO
> >> > > > Pushout", I just put up an animated slides on our web
> site to show =
> >the
> >> > > > relation between SSO, power/gound bounce, signal Return Path
> >> > > Discontinuity
> >> > > > (RPD), and signal timing and waveform degradation.
> >> > > > http://www.sigrity.com/papers/reply20020411/speedxp_ssn.ppt
> >> > > >
> >> > > > And also here is a functional demo software to simulate
> this topic.
> >> > > > http://www.sigrity.com/prod01_demodl.htm
> >> > > > An application example is included (application notes,
> example 7) t=
> >o see
> >> > > the
> >> > > > SSO of 17 nets with gound bounce and RPD, with and
> without decoupli=
> >ng
> >> > > > capacitors. You can change many parameters, such as
> with/without tr=
> >ace
> >> > > > coupling, edge rates, power/ground structures, various decoupling
> >> > > capacitors
> >> > > > (models and locations), different switching bit patterns,
> >> > > even/odd mode. A
> >> > > > good technical paper to reference on this kind SSO
> simulation is "A
> >> > > > Simulation Study of Simultaneous Switching Noise" at:
> >> > > > http://www.sigrity.com/papers/ECTC2001/ECTC_LI1.pdf
> >> > > >
> >> > > > In the case of core logic SSO, the strong power/gound
> transient cur=
> >rents
> >> > > > will generate dynamic EM noise and couple into I/O. This
> phenomenon=
> > is
> >> > > > pointed out on another thread these two days - by Gil
> Gafni on topi=
> >c of
> >> > > > "PCI Buffer Slew Rate", and you can also refer to this
> paper "Integ=
> >rated
> >> > > > Modeling Methodology for Core and I/O Power Delivery" for some
> >> > > discussions:
> >> > > > http://www.sigrity.com/papers/ECTC2001/ECTC_LI2.pdf
> >> > > >
> >> > > > Finally I want to point out, just as Andy said, SSO noise
> >> > > phenomena could
> >> > > > either increase or reduce the signal delay. You can try
> to build an
> >> > > example
> >> > > > with the demo software to show this, even though this time I
> >> > > only provided
> >> > > > the slides for "SSO Pushout".
> >> > > >
> >> > > > Raymond Y. Chen
> >> > > > Vice President, Products and Services
> >> > > > Sigrity, Inc.
> >> > > > ********************************************
> >> > > > 4675 Stevens Creek Blvd. Suite 130
> >> > > > Santa Clara, CA 95051
> >> > > > 408.260.9344 Ext 102
> >> > > > ********************************************
> >> > > > www.sigrity.com
> >> > > >
> >> > > >
> >> > > > > -----Original Message-----
> >> > > > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > > > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
> Ingraham, Andre=
> >w
> >> > > > > Sent: Thursday, April 11, 2002 6:34 AM
> >> > > > > To: linwee70@xxxxxxxxx
> >> > > > > Cc: si-list@xxxxxxxxxxxxx
> >> > > > > Subject: [SI-LIST] Re: SSO pushout
> >> > > > >
> >> > > > >
> >> > > > > > " SSO pushout is a result of multiple drivers
> >> > > > > > switching simultaneously. It impacts signal integrity
> >> > > > > > through adding extra delay to the propagating signal"
> >> > > > > >
> >> > > > > > I understand that we'll have more current in the
> >> > > > > > return path due to simultaneous switching that may
> >> > > > > > cause ground/plane bounce, but couldn't relate that to
> >> > > > > > delay.
> >> > > > > >
> >> > > > > > Can someone explain this  delay, as the text doesn't
> >> > > > > > explain that ?
> >> > > > >
> >> > > > > There are a few mechanisms that result in extra delay.
>  (It isn't
> >> > > > > really a delay in the propagating signal, i.e. wires,
> but rather =
> >in
> >> > > > > the driven signal coming out of the IC outputs.)
> >> > > > >
> >> > > > > One of them is simply this.  When several outputs
> switch from hig=
> >h to
> >> > > > > low, switching current flows in through the signal
> pins and N tim=
> >es
> >> > > > > as much current goes out through the "ground" pins.
> >> > > > >
> >> > > > > The ground system impedance turns this current into
> ground bounce=
> >,
> >> > > > > where on-die "ground" momentarily lifts above board "ground".
> >> > > > >
> >> > > > > For the outputs switching low, the pull-down
> transistor is on, so
> >> > > > > this ground bounce gets added to their outputs.  Imagine simply
> >> > > > > adding a small positive pulse to the outputs, while
> they switch.
> >> > > > > Their falling edges are lifted up slightly, which also has the
> >> > > > > appearance of moving them a little to the right -->
> greater delay=
> >.
> >> > > > >
> >> > > > > So it is really just crosstalk by way of the on-die
> ground bounce=
> >.
> >> > > > >
> >> > > > > The same thing happens for rising edges, except it is
> the VDD or =
> >VCC
> >> > > > > that bounces or sags.
> >> > > > >
> >> > > > > I'm sure there are other mechanisms at work too.  Note that SSO
> >> > > > > can both increase and decrease delays, at least in principle.
> >> > > > >
> >> > > > > Regards,
> >> > > > > Andy
> >> > > > >
> >> > > > > -----Original Message-----
> >> > > > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > > > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Gil Gafni
> >> > > > > Sent: Wednesday, April 10, 2002 12:21 PM
> >> > > > > To: Si-List
> >> > > > > Subject: [SI-LIST] PCI Buffer Slew Rate
> >> > > > >
> >> > > > >
> >> > > > > Hello Experts,
> >> > > > >
> >> > > > > As part of an SSO analysis that we are conducting, we
> noticed an =
> >odd
> >> > > > > behavior of the PCI buffer -
> >> > > > > 1. It looks like it is influenced by the noise on the core Vdd
> >> > > > > (logic side of it) and NOT to the IO Vdd.
> >> > > > > 2. The sensitivity to Vdd core changes is very high; any added
> >> > > > > 100mV of noise can add 1nSec to the pushout.
> >> > > > >
> >> > > > > The bottom line is that with a moderate noise on Vdd
> of 375 mV we=
> > have
> >> > > > > 1nS of push out, and find it very hard to pass (no or
> >> > > negative margins)
> >> > > > > Any recommendations?
> >> > > > >
> >> > > > > Regards,
> >> > > > >
> >> > > > > Gil Gafni
> >> > > > >
> >> > > > >
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