[SI-LIST] Re: Need for SI Service Bureaus?
- From: "Barry Katz" <bkatz@xxxxxxxxxx>
- To: <billh@xxxxxxxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 8 Apr 2002 15:06:18 -0400
Hi Bill,
I have a long list of what the standard SI tools in the industry lack, but
let me pick one of these items to talk about which relates to your comments
concerning the quality of the model vs. the quality of simulator.
To ensure a high-speed design operates properly over a range of component
and board processes, we commonly run hundreds to thousands of simulations on
a bus to account for the entire solution space (ie PVT, lengths,
termination, populations, coupling, variants, etc) that can be encountered
in actual hardware. In each simulation, complex stimulus patterns must be
considered to excite Inter-Symbol Interference (ISI) patterns that can
effect waveforms. The depth of these patterns is a function of bus settling
time and bit time and in some cases functional knowledge of the bus. A
typical stimulus pattern consists of at least 10 edges (not uncommon to
have 50+ edges). Every edge of every simulation must be analyzed for
waveform quality and timing.
Today's high speed edges not only have narrow switching voltage ranges but
often plateau in the transition region. Simply using vmeas, vinl and vinh
typically generate overly conservative results, or generate an excessive
number of waveform rule errors. Waveform processing must not miss any
waveform errors, and must report a very low percentage of false errors while
generating timing results which are always conservative, and be accurate to
20pS. This cannot be done with vendor-supplied vmeas, vinl and vinh numbers.
In fact, there is not even consensus in the industry as to what vmeas, vinl
and vinh mean. The IBIS spec defines 13 different measurement voltage levels
to provide the granularity necessary to illiminate false errors. In fact,
more granuarity/additional checks are required beyond this, but that is a
topic for another discussion. In order to get 20pS timing accuracy,
detailed IO characterization must be performed on the IO buffer transistor
level models to independently determine the voltage swing, slew rate,
frequency, and common mode voltage dependence on timing.
The ability to do IO Characterization of drivers and receivers and rigorous
waveform processing on every edge of every simulation is an example of a
major capablity the most popular tools in the market lack - and is sorely
required by the market. We have found it necessary to incorporate this
level of detail in our tool-set in order to effectively and efficiently
perform high-speed analysis.
Barry
Barry Katz
President & CTO
Signal Integrity Software, Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
O: 978 461 0449 x19
M: 978 618 9078
www.sisoft.com
-----Original Message-----
From: Bill Hargin [mailto:billh@xxxxxxxxxxxxxxxxxxxxxxx]
Sent: Thursday, April 04, 2002 1:22 PM
To: bkatz@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Need for SI Service Bureaus?
Hi Barry:
I hate to dogpile on an old thread like this, but you raise an interesting
question which still remains from a tools standpoint:
> advanced designs. However as 250+ MHz memory systems and 500+ MHz system
> data rates are becoming more common, existing tools and
> techniques no longer
> sufficiently address all of the potential SI problems.
This point is followed by a discussion re. behavioral models, but I would
tend to separate that from the "tools" discussion (i.e., though the two
subjects are related, I draw a line between the quality of the IBIS spec,
for instance, and the quality of semiconductor mfgr's response to the spec).
What are you suggesting that the existing tools lack? (I could provide my
own list, but am curious as to what you or others would like to see on the
tools front ... beyond my own pontifications.)
Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax: 425-702-0305
Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Barry Katz
> Sent: Thursday, April 04, 2002 7:45 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Need for SI Service Bureaus?
>
>
>
> All,
>
> Just catching up my mail. But here are my two cents.
>
> The industry HAS reached the point where companies must revamp their
> approach to signal integrity analysis. This includes
> implementing effective
> tools and methodologies, as well as considering outsourcing.
>
> Until recently, most signal integrity issues could be addressed
> using sound
> design and layout techniques. Simulations were only used for the most
> advanced designs. However as 250+ MHz memory systems and 500+ MHz system
> data rates are becoming more common, existing tools and
> techniques no longer
> sufficiently address all of the potential SI problems. Two of the most
> visible manifestations of this situation are the low quality behavioral
> models supplied for ?free? (?free? is a relative term) by the
> semiconductor
> industry and the increased number of spins before a design is released.
>
> The stark reality is there are manifold issues to consider when
> embarking on
> a new high-speed design. Hspice, IBIS, and Timing libraries must be
> created. Simulations must be run across the entire solution
> space (a broad
> topic in itself) to ensure operation across all corner conditions. The
> resultant mountain of data must be effectively managed AND
> interpreted. And
> of course, the timelines allotted to perform these activities is
> constantly
> shrinking.
>
> In summary, three conditions must exist to ensure that a high-speed design
> project is successful:
>
> 1. A rigorous and thorough design, simulation, and analysis
> methodology must
> be in place
>
> 2. A simulation and analysis environment capable of
> efficiently managing
> thousands of simulations and tens of thousands of edges must be in place
>
> 3. Experienced signal integrity engineers must oversee the application
> aforementioned tools and methodology
>
> The absence of one condition will make design success very
> challenging. The
> absence of two or three conditions will make success nearly impossible.
>
> In short, today?s high-speed designs require a more advanced set of tools
> and techniques. Whether they are deployed internally or
> outsourced are both
> viable options. Outsourcing can provide a significant benefit to design
> teams by allowing them to access a significant breadth of skills and
> experience.
>
> Barry
>
>
> Barry Katz
> President & CTO
> Signal Integrity Software, Inc.
> 6 Clock Tower Place, Suite 250
> Maynard, MA 01754
> O: 978 461 0449 x19
> M: 978 618 9078
> www.sisoft.com
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Shawn Arnold
> Sent: Friday, March 15, 2002 11:47 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Need for SI Service Bureaus?
>
>
> To all list members,
>
> A few of us in Silicon Valley have been discussing the need for a
> Specctraquest "type", tools to be determined by market demands, Signal
> Integrity service bureau, similar to PCB design service bureaus.
>
> After researching the market, we have noticed that there are a
> small handful
> of EMS players that offer this service, but they concentrate on the
> "complete" system build for their top tier clients. We have also noticed
> that a couple of PCB design service bureaus have poked into this area, but
> typically will not pay for quality SI talent to do the job correctly and
> have gotten bad reputations already, the same can be said for a
> few top tier
> PCB fabricators.
>
> Has the market reached a point where outsourcing of these
> typically internal
> resources is a valid business model and under what conditions
> would you use,
> or not use, this type of service?
>
> Please respond, pro or con. All comments welcome.
>
> Sincerely,
> Shawn Arnold
>
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