[SI-LIST] Re: Need for SI Service Bureaus?
- From: Mike LaBonte <mike@xxxxxxxxxxx>
- To: bkatz@xxxxxxxxxx, <billh@xxxxxxxxxxxxxxxxxxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Mon, 08 Apr 2002 20:15:12 -0400
I have to agree with Barry on complex stimulus patterns. These days
I find myself going for the random bit patterns right away. The
difference that it makes in timing results simply can't be overlooked.
Receiver characterization is an issue that needs to be addressed.
D.C. Sessions brought this up years ago, and now I find myself
searching for a way to do it right.
Mike LaBonte
At 03:06 PM 4/8/2002 -0400, Barry Katz wrote:
>Hi Bill,
>
>I have a long list of what the standard SI tools in the industry lack, but
>let me pick one of these items to talk about which relates to your comments
>concerning the quality of the model vs. the quality of simulator.
>
>To ensure a high-speed design operates properly over a range of component
>and board processes, we commonly run hundreds to thousands of simulations on
>a bus to account for the entire solution space (ie PVT, lengths,
>termination, populations, coupling, variants, etc) that can be encountered
>in actual hardware. In each simulation, complex stimulus patterns must be
>considered to excite Inter-Symbol Interference (ISI) patterns that can
>effect waveforms. The depth of these patterns is a function of bus settling
>time and bit time and in some cases functional knowledge of the bus. A
>typical stimulus pattern consists of at least 10 edges (not uncommon to
>have 50+ edges). Every edge of every simulation must be analyzed for
>waveform quality and timing.
>
>Today's high speed edges not only have narrow switching voltage ranges but
>often plateau in the transition region. Simply using vmeas, vinl and vinh
>typically generate overly conservative results, or generate an excessive
>number of waveform rule errors. Waveform processing must not miss any
>waveform errors, and must report a very low percentage of false errors while
>generating timing results which are always conservative, and be accurate to
>20pS. This cannot be done with vendor-supplied vmeas, vinl and vinh numbers.
>In fact, there is not even consensus in the industry as to what vmeas, vinl
>and vinh mean. The IBIS spec defines 13 different measurement voltage levels
>to provide the granularity necessary to illiminate false errors. In fact,
>more granuarity/additional checks are required beyond this, but that is a
>topic for another discussion. In order to get 20pS timing accuracy,
>detailed IO characterization must be performed on the IO buffer transistor
>level models to independently determine the voltage swing, slew rate,
>frequency, and common mode voltage dependence on timing.
>
>The ability to do IO Characterization of drivers and receivers and rigorous
>waveform processing on every edge of every simulation is an example of a
>major capablity the most popular tools in the market lack - and is sorely
>required by the market. We have found it necessary to incorporate this
>level of detail in our tool-set in order to effectively and efficiently
>perform high-speed analysis.
>
>
>Barry
>
>
>Barry Katz
>President & CTO
>Signal Integrity Software, Inc.
>6 Clock Tower Place, Suite 250
>Maynard, MA 01754
>O: 978 461 0449 x19
>M: 978 618 9078
>www.sisoft.com
>
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