[SI-LIST] Re: [SI-LIST]: Wired-AND VS Wired-OR logic
- From: Sunil Kumar <sunilb@xxxxxxxxxxxxxx>
- To: Anand.Kuriakose@xxxxxxxxxx
- Date: Wed, 24 Apr 2002 20:48:42 +0500 (GMT+0500)
Hello Anand,
ECL family can be used in wired-OR fashion.
Outputs of different gates can be tied together
to one common resistor to VEE. The value of
this resistor depends on the number of outputs
connected.
Regards,
Sunil
On Wed, 24 Apr 2002 Anand.Kuriakose@xxxxxxxxxx wrote:
>
>
>
> Hi all,
>
> We can introduce wired-AND logic by connecting 2 or more open-drain (also
> open-collector) outputs together with a single pull-up resister. The logic of
> AND logic results as follows: If one or more of the drivers asserts the output
> to low state (electrically low ), the equivalent output is low, which is how
> an
> AND gate functions. Also the connected signals have to be active-low signals.
>
> I have seen many documents refering to the above scenario as wired-OR logic.
> It
> doesnt make sense. Also the PCI spec 2.2, sec2.1 refers to O/D signals (ex
> INTX#
> and SERR#) as to be capable of introducing wired-OR logic.
>
> So what is wired-OR logic? How do we realise this logic? Does the active level
> of the connected signals make the difference?
>
> Also one more question. When it comes to wired-AND logic, only one device can
> assert its output low. We cannot have more than one device asserting its
> output
> low simultaneously. Am i right in saying so. If yes, is this allowed in
> wired-OR
> logic.
>
> Thanx in advance for all the valuable inputs.
>
> Regards,
> Anand Kuriakose.
>
>
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