[SI-LIST] Series Termination Question

I'm presently designing a board that will be used by company "X". =
Basically, this is to be one of our storage routers in a form factor =
that will fit within their product. In going though the schematics to =
ensure that we're going to be giving them what they want, their =
regulatory engineer made a request that I can't quite get my mind =
around. I was hoping that someone could give me some insight into this =
request so I can understand why he is asking for this (i.e., what good =
does it actually do).

Normally, we use series terminators in this fashion with R chosen based =
on driver and trace impedance (as well as what seems to work in the =
lab):
             R1     __________
       |\__/\/\/\__|  Trace   |__|\
Driver |/          |__________|  |/  Receiver


But the company "X" regulatory guy is asking for this on clock signals:

             R2     __________     R3
       |\__/\/\/\__|  Trace   |__/\/\/\__|\
Driver |/          |__________|          |/  Receiver


So, what would be the advantage of using two resistors where one seems =
to do the job? And it seems that, if we went with the second circuit, R2 =
+ R3 =3D R1 but what other constraints would make sense? For clock =
signals, we have 40 MHz, 66 MHz, 85 MHz, and 100 MHz.


I'm rather caught between not understanding the utility of his request =
and two basic business axioms:
* The customer is always right.
* Give the customer what she needs (not necessarily what she wants).

Thanks in advance for your advice.

_______________________________________
|                                      |
| Bill Reams  - Sr. Hardware Engineer  |
| 512-928-7201 (direct)                |
| 512-349-0300 (Main)                  |
| breams@xxxxxxxxxxxxxx (e-mail)       |
|______________________________________|

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