[SI-LIST] PCI Timing Q?
- From: Brahim Koudssi <brahim@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 29 May 2002 07:43:23 -0700
Dear SI-List members,
I need help in answering two questions related to PCI bus transactions,
the specs. do not tell the whole story.
Tval is measured as the delay time between clk(i) and when the data is
valid, clk(i) precedes the data,
Tval is measured at the driver output.
1. Once the signals, clk and data arrive at the receiver, which clock
samples the data?
Is it clk(i) or clk(i-1)?
2. The clock signal is from a board to the PCI expansion card, how's
the data sampled by a board
when the data is originating from the card?
Thank You,
Brahim koudssi
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