Posts for si-list, 09-2006

Browse: Last Month: 08-2006 Main Archive Page Next Month: 10-2006

» [SI-LIST] RF PCB & Circuit Design -
» [SI-LIST] Reliability Issue ATCA Mechanical Ejector engaging the Handle Switch -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Re: An SI engineer you should know -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Aspect Ratio -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Re: Aspect Ratio -
» [SI-LIST] Aspect Ratio -
» [SI-LIST] Public Siemens IBIS website online -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] FW: EPMC announcement - 2006 short course -
» [SI-LIST] Public Siemens IBIS website online -
» [SI-LIST] Re: An SI engineer you should know -
» [SI-LIST] An SI engineer you should know -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: Rise time impact on input buffer -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: Question for CST Microwave Studio experts -
» [SI-LIST] Test -
» [SI-LIST] Q. on DDR rise time measurements -
» [SI-LIST] Re: Question for CST Microwave Studio experts -
» [SI-LIST] Re: Question for CST Microwave Studio experts -
» [SI-LIST] Question for CST Microwave Studio experts -
» [SI-LIST] Asian IBIS Summit (China) - Fifth Announcement -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: DDR interface -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] DDR interface -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Lossy Line Simulation DDR Signals and HSPICE netlist generation -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Upcoming Class on SI and PCB Design at UC Berkeley -
» [SI-LIST] Re: Dual referenced stripline? -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Rndom reset problem -
» [SI-LIST] Re: Intermittent issue with the board -
» [SI-LIST] Re: Intermittent issue with the board -
» [SI-LIST] Re: Windows based IBIS Parser -
» [SI-LIST] Re: Intermittent issue with the board -
» [SI-LIST] Intermittent issue with the board -
» [SI-LIST] Re: di/dt transfer function measurement with Network Analyzer -
» [SI-LIST] di/dt transfer function measurement with Network Analyzer -
» [SI-LIST] Re: Windows based IBIS Parser -
» [SI-LIST] Windows based IBIS Parser -
» [SI-LIST] Re: parallel plane strange results -
» [SI-LIST] Re: Signal Integrity Wiki -
» [SI-LIST] Signal Integrity Wiki -
» [SI-LIST] Dual referenced stripline? -
» [SI-LIST] Digital Bench Characterization project in Sunnyvale -
» [SI-LIST] Re: Memory Signal Integrity -
» [SI-LIST] Re: Memory Signal Integrity -
» [SI-LIST] Re: parallel plane strange results -
» [SI-LIST] Re: parallel plane strange results -
» [SI-LIST] Memory Signal Integrity -
» [SI-LIST] Re: parallel plane strange results -
» [SI-LIST] Re: parallel plane strange results -
» [SI-LIST] parallel plane strange results -
» [SI-LIST] Re: HSTL and SSTL -
» [SI-LIST] Re: HSTL and SSTL -
» [SI-LIST] Re: DDR2 SO-DIMM Gerber files -
» [SI-LIST] HSTL and SSTL -
» [SI-LIST] Comments on PI analysis tools (Ansoft SI wave & Sigrity PI) -
» [SI-LIST] DDR2 SO-DIMM Gerber files -
» [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] -
» [SI-LIST] Re: Rise time impact on input buffer -
» [SI-LIST] Re: Rise time impact on input buffer -
» [SI-LIST] Re: Rise time impact on input buffer -
» [SI-LIST] Rise time impact on input buffer -
» [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] -
» [SI-LIST] hot-carrier effect on IC reliability -
» [SI-LIST] Signal Integrity Engineering Manager -
» [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] -
» [SI-LIST] Re: Target Impedance in PCB power plane... -
» [SI-LIST] Re: Target Impedance in PCB power plane... -
» [SI-LIST] Re: Target Impedance in PCB power plane... -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Target Impedance in PCB power plane... -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] -
» [SI-LIST] OUTPUT IMPEDANCE CALCULATION [IBIS] -
» [SI-LIST] Re: Post Layout Simulation -
» [SI-LIST] Looking for Myun-Joo Park -
» [SI-LIST] Re: Hot monday dother -
» [SI-LIST] Re: Spreading Inductance -
» [SI-LIST] Re: AMSN god -
» [SI-LIST] Re: News for AMSN sun -
» [SI-LIST] Re: Post Layout Simulation -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Signal Integrity Job Opportunities at Broadcom -
» [SI-LIST] Re: Post Layout Simulation -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Spreading Inductance -
» [SI-LIST] Re: Post Layout Simulation -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Post Layout Simulation -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Hspice: use S-Parameter model extracted from CST -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Re: Routing Parallel vs. Paralell -
» [SI-LIST] Routing Parallel vs. Paralell -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: Emc_FTT -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Asian IBIS Summit (Japan) Third Announcement -
» [SI-LIST] Re: Emc_FTT -
» [SI-LIST] Re: Emc_FTT -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Job Opening - Xilinx -
» [SI-LIST] Recommendation on a good HDI PCB proto house suitable for 0.5mm BGAs with SI -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: Emc_FTT -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: Voltage & Prepeg thickness -
» [SI-LIST] set SI-LIST vacation -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Consulting opportunity -
» [SI-LIST] High voltage & via size -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Asian IBIS Summit (China) Fourth Announcement -
» [SI-LIST] Re: List of PCB characterization/Modelling vendors in Bay Area -
» [SI-LIST] List of PCB characterization/Modelling vendors in Bay Area -
» [SI-LIST] Re: Measure flight time with TDR -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: Measure flight time with TDR -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: PCB High Voltage -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Measure flight time with TDR -
» [SI-LIST] Emc-ftt -
» [SI-LIST] Emc_FTT -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] Re: FW: PCB High Voltage -
» [SI-LIST] Pcb High Voltage -
» [SI-LIST] Pcb High Voltage -
» [SI-LIST] FW: PCB High Voltage -
» [SI-LIST] PCB High Voltage -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Do you use board-level signal integrity simulation? -
» [SI-LIST] Re: Voltage & Prepeg thickness -
» [SI-LIST] Re: Voltage & Prepeg thickness -
» [SI-LIST] Re: ICEM model -
» [SI-LIST] Re: HighVoltage -
» [SI-LIST] Re: Voltage & Prepeg thickness -
» [SI-LIST] ICEM model -
» [SI-LIST] Re: Voltage & Prepeg thickness -
» [SI-LIST] HighVoltage -
» [SI-LIST] high voltage -
» [SI-LIST] Antw: Voltage & Prepeg thickness -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] Voltage & Prepeg thickness -
» [SI-LIST] PCIe load board -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Out of office -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] AMD Signal Integrity Job Opportunity -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] EBD Files -
» [SI-LIST] Watch PPTL on Thursday Sep 7 -
» [SI-LIST] Fw: OT: SPAM! -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] fwd: Watch PPTL on Thursday September 7, 2006 -
» [SI-LIST] Re: How to get RLC equivalent model from S parameter of the passive component -
» [SI-LIST] How to get RLC equivalent model from S parameter of the passive component -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: We need help -
» [SI-LIST] Out of office -
» [SI-LIST] Re: We need help -
» [SI-LIST] Re: some help needed: Re: Testing chips with system level specs -
» [SI-LIST] some help needed: Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Out of office -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: EU RoHS' (lead free initiative) effect on SI -
» [SI-LIST] Out of office -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] for you to have it GCM E -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: minimum and maximum tracelength -
» [SI-LIST] which type of power(core logic power or I/O power) has a high priority -
» [SI-LIST] Re: minimum and maximum tracelength -
» [SI-LIST] Re: minimum and maximum tracelength -
» [SI-LIST] Re: minimum and maximum tracelength -
» [SI-LIST] Re: minimum and maximum tracelength -
» [SI-LIST] Out of office -
» [SI-LIST] Out of office -
» [SI-LIST] minimum and maximum tracelength -
» [SI-LIST] SI related jobs at Mobilygen; -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: ddr2 timing simulation -
» [SI-LIST] Re: EU RoHS' (lead free initiative) effect on SI -
» [SI-LIST] Re: We need help -
» [SI-LIST] We need help -
» [SI-LIST] EU RoHS' (lead free initiative) effect on SI -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? -
» [SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? -
» [SI-LIST] Re: Impedance without a reference plane -
» [SI-LIST] Re: Impedance without a reference plane -
» [SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? -
» [SI-LIST] AW: Re: Testing chips with system level specs -
» [SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Re: Impedance without a reference plane -
» [SI-LIST] Re: Testing chips with system level specs -
» [SI-LIST] Testing chips with system level specs -
» [SI-LIST] Re: Timing equations - help -
» [SI-LIST] Re: Current Bias Chip -
» [SI-LIST] Re: Impedance without a reference plane -
» [SI-LIST] Impedance without a reference plane -
» [SI-LIST] Re: Timing equations - help -
» [SI-LIST] Current Bias Chip -
» [SI-LIST] stocksubj2 -
» [SI-LIST] About Generator short circuit current for EIA/TIA-644(LVDS) specification -
» [SI-LIST] About Generator short circuit current for EIA/TIA-644(LVDS) specification -
» [SI-LIST] Asian IBIS Summit (Japan) Announcement -
» [SI-LIST] Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: What do you do? -