[SI-LIST] FW: EPMC announcement - 2006 short course
- From: "Jin Zhao" <jzhao@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Sep 2006 17:49:25 -0700
FYI=20
-----Original Message-----
From: Jay Tsai [mailto:jay_tsai@xxxxxxxxx]=20
Sent: Wednesday, September 27, 2006 4:11 PM
To: jt
Subject: EPMC announcement - 2006 short course
CIE-SF chapter and Co-sponsor San Jose State University announce the =
year
2006 Annual Short Courses. Four 2-hour technical/career classes are
scheduled in career planning, IC electronic packaging, power integrity
simulation with IBIS and signal integrity (SI) and power integrity (PI)
design guideline and process.=20
Courses will be presented by renowned experts from industry. Both
introductory and in-depth technical aspects will be discussed. Classes =
will
be held from October 7th to 28th, 2006, every Saturday afternoon from =
2:00
pm to 4:00 pm at San Jose State University, Engineering Building. =20
CIE-SF chapter and Co-sponsor San Jose State University announce the =
year
2006 Annual Short Courses. Four 2-hour technical/career classes are
scheduled in career planning, IC electronic packaging, power integrity
simulation with IBIS and signal integrity (SI) and power integrity (PI)
design guideline and process. Courses will be presented by renowned =
experts
from industry. Both introductory and in-depth technical aspects will be
discussed. Classes will be held from October 7th to 28th, 2006, every
Saturday afternoon from 2:00 pm to 4:00 pm at San Jose State University,
Engineering Building. Checking in time will be 1:30 pm to 2:00 pm.
Fees: Free to San Jose State University students/faculties
For CIE member, $20 each section, $60 for entire package.
For non-CIE member, $30, each section, $100 for entire package.
Please visit CIE-SF website at http://www.cie-sf.org/ for more detail
information.
Pre-registration is highly recommended, please email to
CIE_shortcourse2006@xxxxxxxxx for registration.
Schedule of the short courses:
Course=20
EPMC01:=20
The molding of self in a High-Tech, Multicultural Environment Mr. =
Bryn
A. Higgins, M.A.C.R. 10/07/2006
Course EPMC02:=20
Polymers in Electronic Packaging =20
Dr. Jack Zhang
10/14/2006Course=20
Course EPMC03:=20
Power Integrity Simulation with IBIS: BIRD95 and its implementation
Dr. Zhiping Yang =20
10/21/2006
Course=20
EPMC04:=20
Signal Integrity (SI) and Power Integrity (PI) Design Guideline and =
Process
Dr. Huabo Chen =20
10/28/2006
Location: San Jose State University, Engineering Building, Auditorium or =
285
Lecture Hall, (Engineering Building is located on San Femando St. =
between
7th and 8th street.
Map: http://www.sjsu.edu/about_sjsu/docs/SJSU_campus_map.pdf
EPMC01: The Molding of Self in a High-Tech, Multicultural Environment
In this session, the following topics would be explored: =20
* The demands of the high-tech industry on the individual self
* The demand of and on managers, co-workers and subordinates
* Personality and culture in the working environment
* The truth behind conflict and misunderstandings
* The secret to knowing one's self and others
* What makes us who we are, the modeling of self
* How to shine and make others shine
Author Biography:
Bryn A. Higgins: Product Manager/ Molding Compounds/ Shin-Etsu Chemical =
Co,
Ltd. Bryn previously had also worked at Sumitomo Plastics (Sumitomo
Bakelite), handling molding compounds, glob-top materials, under-fill
materials and die attach paste, as well as at Nitto for carrier tape, =
dicing
tape, and back grinding tapes. Bryn received a Master of Art (MA) =
degree in
Conflict Resolution.
EPMC02: Polymers in Electronic Packaging
In this session, the following topics would be explored: =20
* The market analysis of electronic packaging industry, particularly on
packaging materials
* Review of processing and characterization of polymers
* Polymers are used in electronic packaging, emphasizing on thermoset
materials, such as molding compounds, die attaches, and under fills
* Future challenges, impact of reintegration of front end and back end =
to
polymer materials
Author Biography:
Jack Zhang is a materials scientist at Henkel Technologies. He has more
than ten years experience on research and development of electronics
materials. His career interest is to combine his expertise in =
technology
with strategic product management and marketing.
EPMC03: Power Integrity Simulation with IBIS: BIRD95.6 and its
implementation
IBIS models are widely used in I/O related signal integrity simulations =
due
to its simplicity, fast simulation speed and protection of vendor=A1=A6s
intellectual properties. Since all information (I-V and V-T tables) in
existing IBIS model is extracted at condition where all power supply are
ideal, it is well known that IBIS models are not accurate for power
integrity related simulations. With ever-increasing speed, frequency,
density, and power, as well as decreasing circuit dimensions and logic
levels, power integrity issues are becoming more and more critical in
high-speed system designs. Some industry experts claim that power =
integrity
is becoming the number one issue that the integrated circuit and =
electronics
industry faces, starting from the 0.13um process node. =20
Knowing the problems associated with existing IBIS model, by the author =
and
his Cisco colleagues firstly drafted BIRD95.1 (Buffer Issue Resolution
Document) on 12/13/2004 to address IBIS accuracy issue when power supply =
is
nonideal. With the help from other industry experts, the BIRD95 =
proposal
was revised several times. The final version of BIRD95.6 was accepted =
by
IBIS standard committee on 10/7/2005. This short course is intended to
review the IBIS and other macromodeling techniques to address power
integrity related simulation issues at the beginning. BIRD95 and its
implementation in HSPICE will be explained in detail. The progresses of
IBIS and other potential issues related to IBIS will be briefly =
discussed at
the end of the short course. The targeted audiences are high-speed =
digital
circuit designers, signal integrity and power integrity engineers, and
high-speed EDA tool developers.
Author Biography:
Zhiping Yang currently is working in Nuova Systems as a Signal Integrity
Engineer. Before he joined Nuova Systems, he was a Principal Signal
Integrity Engineer at Apple Computer and a Technical Leader at Cisco =
System
Inc. His research interests include signal integrity and power =
integrity
methodology development for Die/Package/Board co-design, application of
embedded passives, extraction of material properties at high frequency, =
and
high-speed differential signaling technology.? He is actively involved =
with
IBIS (I/O Buffer Information Spec) standard activities. His research =
work
in power integrity greatly increases IBIS model=A1=A6s simulation =
accuracy under
nonideal power supply condition. IBIS standard committee accepted =
BIRD95.6
proposal on 10/7/2005, which was coauthored by he and his colleagues in
Cisco Systems and Teraspeed Consulting group. He has published more =
than 20
research papers and has 7 pending patent applications. He is a senior =
IEEE
member. He received his Ph.D. from the University of Missouri-Rolla, =
and
his B.S. and M.S. from Tsinghua University, Beijing.
EPMC04: Signal Integrity (SI) and Power Integrity (PI) Design Guide =
Line
and Process
As interfaces run at higher speeds with faster edge rates, ensuring =
signal
integrity (SI) and power integrity (PI) is critical to successful system
implementation. This presentation begins with reviewing some basic =
concepts
of electrical modeling. It then introduces the SI process and design
guidelines. It reveals how SI engineer interact with chip designer, =
package
designer and PCB designer to make the right design tradeoff and meet the
timing budget. In the end it explains some best practices of signal =
routing
and power ground design. =20
Author Biography:
Dr. Huabo Chen is a senior signal integrity engineer in Nvidia. She has =
been
responsible for the signal integrity design of two generations of high =
end
GPUs and chipsets in the past few years. She received Ph.D. in =
Electrical
Engineering from University of California in Santa Cruz.
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