[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing?

George, since the multiple questions commonly come up:

1) What are the benefits of thin and/or loaded dielectrics, and
2) What configurations, and / or processes are covered by existing patents, and
3) Who is licensed to use what property

It might be very helpful to Sanmina and the industry at large to 
publish answers to those questions as they pertain to at least 
Sanmina's portfolio.  It is not always evident to folks how even 
though the concept of parallel plate techniques is an old idea that 
what the patents cover is largely the processing methods necessary to 
realize thin plate separations in a production environment.  This 
gets further clouded when from time to time completely invalid patent 
claims make their way through the industry, like Palm's ill advised 
recent efforts to enforce claims of a gated space multiplexor, shown 
to be practiced art from the 1960's.

I am a big believer in thin dielectrics for a number of applications 
and strongly recommend them where they make sense to Teraspeed 
customers.  More information will help speed propagation of the well 
demonstrated technical merits without unnecessary legal entanglements.

Regards,


Steve.
At 05:43 PM 9/6/2006, George Dudnikov wrote:
>  Good Afternoon,
>      My SI engineers forwarded the thread regarding thin dielectrics and
>Buried Capacitance. I read through it and felt it appropriate to post a
>message that maybe clarified the issue as it appears that some of the
>opinions posted would potentially give folks the wrong guidance. Since
>this is a technical forum, I will restrict any legal discussion to a
>brief and high level description. I would encourage, however, any
>designer working with thin plane dielectrics in their PCBs to check with
>their own IP professionals regarding their applications and not rely on
>a magazine article or the personal opinion of one SI consultant.
>There are 9 US patents consisting of 184 claims covering Buried
>Capacitance (tm) exclusively owned by HSCI, subsidiary of Sanmina-SCI.
>The claims cover applications, structures and methods of fabrication for
>the Buried Capacitance(tm) technology. In addition, there are 22 foreign
>patents covering the technology, including patents in EU,  Taiwan,
>Japan, Korea and China.
>  As well known, while a patent allows for the owner to make or  have
>made products covered by the patent claims, it gives the right to
>prevent others from making the product. However, like other technology
>companies, HSCI is not precluding the use of its patents and offers the
>patented products to the industry under reasonable licensing
>arrangements. In the case of BC, we currently have 30 licensees
>representing some of the largest and technologically leading PCB
>fabricators in the world. In addition, there are 7 licensed laminators
>who make material under strict quality and performance guidelines
>resulting in the highest level of reliability and, as mentioned by one
>SI List member, ZBC carries with it recognition by Telcordia for use in
>telecom products for GR78 compliance..
>
>It's safe to assume that all of HSCI licensees had conducted their legal
>due diligence on the Buried Capacitance patent portfolio before agreeing
>to a license. A list of licensed PCB fabricators and material laminators
>can be found at:
>  http://www.sanmina-sci.com/Solutions/pcb_fab.html .  Our attorneys will
>not allow me to go into detail, but our response to the question on
>patent enforcement is that the BC patents have in fact stood up through
>several legal actions and challenges. It's difficult to understand why
>someone would  go through the effort, risk and financial burden of
>challenging patents in court when the technology has such a wide market
>acceptance, proven performance record, robust supply chain and
>demonstratable ROI..
>
>
>  ZBC 2000 (r) is in fact a 2 mil material and by far the market leader
>in embedded  capacitance materials being specified by all major OEMs and
>used over the last decade in millions of printed circuit boards. ZBC
>2000 provides about 500 pf/sq.in of capacitance at an easily justifiable
>cost/performance ratio. Contrary to the incorrect assumption, the patent
>portfolio covers dielectric thickness ranges up to 4 mils.  Use of 2.4
>or 2.5 mil cores does not avoid the claims covered by the patents.
>There is a ZBC 1000 ( 1 mil)  material that is also available, but due
>to a  limitation on breakdown voltage capability, is not fully
>commercialized at the moment.
>
>In recent years, the need for thinner P/G  dielectrics ( reduced
>inductance and plane resonance) and higher  interplane capacitance
>density  has lead to the development  and adoption in system design of
>film based dielectrics ( some loaded with barium titanate  nano-powders
>to increase Dk and capacitance) . These dielectrics typically range from
>8 microns to 24 microns in thickness and can be loaded to provide over
>11 nf/sq.in of capacitance. There are 2 licensed manufacturers of these
>materials for Buried Capacitance : Oak Mitsui who market their materials
>under the Faradflex trademark and Dupont Electronic Technologies, who
>market under the HK-4 and Interra trademarks. Both of these materials
>can be shown to have higher reliability and better manufacturability
>than some of the unlicensed materials mentioned, something that
>designers must consider when working on a new layout. A material may
>look great in the marketing literature, but if it cannot be built into a
>PCB in volume with high yields and efficient processing, or meet system
>performance or regulatory standards, it doesn't matter if there are
>patents or not, the material won't work past the proto stage.
>
>This SI List thread started with a question from Gilles regarding using
>prepreg dielectrics thinner than 4 mils to achieve greater interplane
>capacitance. Yes, there is an HSCI patent that covers this application (
>US 5,261,153), but again, the real concern has to do with volume
>reliability and performance (a concern identified in his original
>question). Currently, this patent is not licensed to anyone as part of
>our BC portfolio because of potential quality and long term reliability
>concerns. . As was previously mentioned on this thread, single ply
>dielectrics can be risky business when you think about voltage
>differential and the potentially catastrophic effect of any type of
>inclusion or conductive path between planes. Prepreg dielectrics have
>exposure to foreign material and inclusions during the glass yarn
>manufacturing, prepreg coating and PCB lamination processes. There is a
>significantly elevated risk of yield loss due to hard power ground
>shorts or field issues due to latent P/G shorting from electromigration.
>One of the benefits of licensed ZBC materials, in addition to certain
>structural specifications, is the requirement to hypot test the cores
>and finished PCBs to a minimum of 500VDC breakdown voltage using
>prescribed ramp rates and dwells. Film based dielectrics have the
>advantage of eliminating the glass weave and have even better voltage
>breakdown performance.
>  We have been working on ways to improve the reliability and validation
>of prepreg defined dielectrics, but currently would recommend using core
>stackups as a better option and would consider licensing only low
>voltage applications.
>If anyone needs more information or details on this subject, please send
>a note to embeddedpassives@xxxxxxxxxxxxxxx .  There are engineers
>available who can assist  with design related SI questions, stackups
>and/or material selection for RoHS. We have a lot of data on high
>frequency applications and removal of bypass caps.  Feel free to check
>out additional information on our website or contact any one of our
>licensed material suppliers or PCB fabricators directly
>
>George Dudnikov
>SVP& CTO
>Sanmina-SCI
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of B Simonovich
>Sent: Tuesday, September 05, 2006 11:19 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: What is the acceptable minimum pre-pregthickness
>for volume manufacturing?
>
>The Sanmena-SCI licencing for burried capacitance is for ZBC-2000(TM)
>laminates. This laminate is a specially constructed copper cladded FR4
>core with a single ply of 106 or 6060 style pre-preg having a dielectric
>thickness of 0.002 inches (+/- 0.0005 inches) after cross-sectioning.
>The drum side (smooth side) of the copper foil contacts the prepreg
>while the rough matte surface is exposed. Depending on the actual
>prepreg used, the distributed capacitance is approx 500pf to 550pf/sq
>inch. It is treated like any other core within a PCB stackup and is
>compatible with the normal PCB fabrication process. Using ZBC200(TM)
>material allows you to pass Bell Core GR-78-CORE with exception clause.
>Specifying dielectric less than 0.004" without using ZBC200(TM) laminate
>or equivalent means you need to do the work to have the exemption if it
>matters to you.
>
>Regards,
>
>Bert Simonovich
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Lee Ritchey
>Sent: Tuesday, September 05, 2006 12:09 PM
>To: Steve Weir; John Andresakis; Gilles Aminot; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: What is the acceptable minimum pre-pregthickness
>for volume manufacturing?
>Steve,
>Good eye! Somehow, I typed the wrong date in my reference library index.
>That is the article.
>It is curious that thousands of PCBs have been designed with planes
>separated by thin dielectrics for the purpose of forming planae
>capacitance without any of them being challenged as violating these
>patents.
>Lee
>
> > [Original Message]
> > From: steve weir <weirsi@xxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; Andresakis, John
><John.Andresakis@xxxxxxxxxxxxx>; Gilles Aminot <aminotg@xxxxxxx>;
>si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> > Date: 9/4/2006 11:39:51 PM
> > Subject: [SI-LIST] Re: What is the acceptable minimum
> > pre-pregthickness
>for volume manufacturing?
> >
> > Lee, did you mean August 2004? Joel's piece can be found on the 3M web
>site.
> >
> >
>http://multimedia.mmm.com/mws/mediawebserver.dyn?6666660Zjcf6lVs6EVs66S7
>3jCO
>rrrrQ-#search=%22%22printed%20circuit%20design%22%20%2B%22the%20history%
>20of
>%20embedded%22%22
> >
> > Regards,
> >
> >
> > Steve.
> > At 11:34 AM 9/4/2006, Lee Ritchey wrote:
> > >There was an article in the August 03 issue of Printed Circuit Design
> > >magazine titled "The History of Embedded Distributed Capacitance," by
>Jole
> > >Pfeiffer of 3M showing that the patents held by Sanmina-SCI are
> > >invalid
>due
> > >to the existance of both prior art and prior patents.
> > >
> > >
> > > > [Original Message]
> > > > From: Andresakis, John <John.Andresakis@xxxxxxxxxxxxx>
> > > > To: Gilles Aminot <aminotg@xxxxxxx>; si-list@xxxxxxxxxxxxx
> > ><si-list@xxxxxxxxxxxxx>
> > > > Date: 8/30/2006 8:45:29 PM
> > > > Subject: RE: [SI-LIST] What is the acceptable minimum pre-preg
>thickness
> > >for volume manufacturing?
> > > >
> > > > Gilles,
> > > >
> > > > Depending on the copper weight and the area of copper retained,
> > > > you
>can
> > >use
> > > > lower than 4 mils. The situation is that Sanmina has a patent for
> > >forming a
> > > > capacitor plane in-situ, which is what you are trying to do. It
> > > > makes
>no
> > > > difference whether you purchase a 2 mil core or use 2 mil prepreg
>between
> > >a
> > > > power and ground plane during pressing, it still is covered by
>patents.
> > > >
> > > > Best Regards,
> > > >
> > > > John Andresakis
> > > > Oak-Mitsui Technologies
> > > > (518) 686-8088
> > > >
> > > > -----Original Message-----
> > > > From: Gilles Aminot
> > > > To: si-list@xxxxxxxxxxxxx
> > > > Sent: 8/30/2006 10:44 PM
> > > > Subject: [SI-LIST] What is the acceptable minimum pre-preg
> > > > thickness
>for
> > > > volume manufacturing?
> > > >
> > > > Hi All,
> > > > Is there a PCB guru out there who can tell me what is the minimum
> > > > recommended pre-preg thickness for volume manufacturing? I want to
> > > > increase inter-plane capacitance by reducing the pre-preg
> > > > thicnkess between my power and ground planes. Currently we are
> > > > using a pre-preg thickness of 4mils. I did some research and found
> > > > that pre-preg comes
>in
> > > > thicknesses as low as 2mils. Can we go as low as 2mils between
> > > > planes
>on
> > > > an FR-4 PCB designed for RoHS compliance and still have a board
> > > > which can be reliably built in high volume?
> > > >
> > > > Thanks in advance for your replies.
> > > >
> > > > Kindest Regards,
> > > > Gilles Aminot
> > > >
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