[SI-LIST] Rise time impact on input buffer

Hi all,

It's clear that fast rise(short) will create EMC problem or shoot =
problem if
it is not properly terminated? Will rise time have any impact on the
receiver side, I mean sensing in the logic level by receiver? Why are
Manufacturers of IC specifying receiver rise or fall time constraints? =
What
is the rise time impact in the receiver side?


    __/----     __/----=09
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|/                     |/
Driver           Receiver

One of my guess is Slow rise (long) time signal will dissipate more =
power in
the buffer stage of CMOS IC and leads to metastability in the next =
stage. Is
my guess correct?

Thanks in advance.

Regards,
Padmanaban
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