[SI-LIST] Re: Rise time impact on input buffer

Hi padmanaban,

I think the receiver side rise or fall time constraints are specified
such that any edge in that range will not result in a shoot that is not
in the maximum specified shoot levels of the receiver IC and will be
detected as transmitted.If iam wrong, please correct me.

kranthi

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Padmanaban Balamuraleedharan - TLS, Chennai
Sent: Wednesday, September 20, 2006 12:42 PM
To: silist
Subject: [SI-LIST] Rise time impact on input buffer


Hi all,

It's clear that fast rise(short) will create EMC problem or shoot =
problem if it is not properly terminated? Will rise time have any impact
on the receiver side, I mean sensing in the logic level by receiver? Why
are Manufacturers of IC specifying receiver rise or fall time
constraints? = What is the rise time impact in the receiver side?


    __/----     __/----=09
|\______________|\
|/                     |/
Driver           Receiver

One of my guess is Slow rise (long) time signal will dissipate more =
power in the buffer stage of CMOS IC and leads to metastability in the
next = stage. Is my guess correct?

Thanks in advance.

Regards,
Padmanaban
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