[SI-LIST] Re: DDR interface

Hi,
 
Yes you right. Actually JEDEC specify relatively wide range : from 75%
to 125% of clock cycle.
 
 
 
Best regards,
Edi Fraiman
 
 
 
        -----Original Message-----
        From: Karthik Raj [mailto:karthikraj.g@xxxxxxxxx] 
        Sent: Tuesday, September 26, 2006 10:30 AM
        To: Fraiman, Edi
        Subject: Re: [SI-LIST] DDR interface
        
        
        Hi,
         
        I am not very sure about DDR but in DDR2 there is a spec that
determines the CLK - DQS relation called tDQSS. You may need to make
sure that your lengths meet this timing.
         
        Rgds,
        Karthik
        
         
        On 9/26/06, Fraiman, Edi <Edi.Fraiman@xxxxxxxxxx> wrote: 

                Hi all,
                
                I have question about DDR interface layout.
                I understand that during PCB layout the DQS (data
strobe) should be 
                routed with same length as DQ (data), DQM signals and
                Address bus and control signals (RAS,CAS, CKE,WE,CS)
should be aligned
                to clock.
                But I do not understand what relationship (what the
maximum difference
                in length) between  DQS and CLOCK.
                Could you please advise?
                
                =20
                Best regards,
                Edi Fraiman
                =20
                =20
                =20
                
                
                
                
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