[SI-LIST] DDR interface

Hi all,

I have question about DDR interface layout.
I understand that during PCB layout the DQS (data strobe) should be
routed with same length as DQ (data), DQM signals and
Address bus and control signals (RAS,CAS, CKE,WE,CS) should be aligned
to clock.
But I do not understand what relationship (what the maximum difference
in length) between  DQS and CLOCK.
Could you please advise?

=20
Best regards,
Edi Fraiman
=20
=20
=20




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