[SI-LIST] hot-carrier effect on IC reliability

Dear all

In our design, the overshoot is always a critial element. According to the 
paper, overshoot could degrate the delaytime of n-MOS or p-MMOS. Is there a 
design-guideline to check whether the overshoot is acceptable or not? In 
another word, there is a buffer of 3.3V. The simulated overshoot is about 4.1V. 
How to check it is good or not? What kind of information is necessary?

Any advice will be helpful.

Best Regards

Zhangkun
2006.9.20

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