Posts for si-list, 08-2006

Browse: Last Month: 07-2006 Main Archive Page Next Month: 09-2006

» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: ddr2 timing simulation -
» [SI-LIST] Re: ddr2 timing simulation -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Theory behind extending DVI-I & USB cables beyond their rated length -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] FW: FW: Electrical Requirements for Packaging class -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Re: 回复： DDR-simulation -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] free signal integrity seminar coming to your area soon -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Spice Noise Analysis -
» [SI-LIST] ddr2 timing simulation -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: Timing equations - help -
» [SI-LIST] Re: Hyperlynx Results interpretation -
» [SI-LIST] Re: Timing equations - help -
» [SI-LIST] Timing equations - help -
» [SI-LIST] What is the acceptable minimum pre-preg thickness for volume manufacturing? -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Job Opening - SI CW Position -
» [SI-LIST] Hyperlynx Results interpretation -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] Re: 6 port via -
» [SI-LIST] 6 port via -
» [SI-LIST] Re: Expresscard 1.0 Thermal Spec -
» [SI-LIST] Join the Anatrim revolution -
» [SI-LIST] hi -
» [SI-LIST] PCB Fabrications -
» [SI-LIST] Re: flex circuit & chip scale basics -
» [SI-LIST] Asian IBIS Summit (China) Third Announcement -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Chips, Circuits to extend length of DVI-I, DVI-D, DVI-A and USB cables -
» [SI-LIST] Re: SIwave error : BAD_INPUT -
» [SI-LIST] Re: Expresscard 1.0 Thermal Spec -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] SIwave error : BAD_INPUT -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] What is the difference between "non dry circuit test" and -
» [SI-LIST] Re: flex circuit & chip scale basics -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] please, recommend a RELAY to use in Device Test Industry -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Expresscard 1.0 Thermal Spec -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] Re: What do you do? -
» [SI-LIST] What do you do? -
» [SI-LIST] Re: What is the difference between "non dry circuit test" and "dry circuit test" -
» [SI-LIST] What is the difference between "non dry circuit test" and "dry circuit test" -
» [SI-LIST] Re: SATA Cable Assembly Models -
» [SI-LIST] flex circuit & chip scale basics -
» [SI-LIST] Re: Phase jitter vs. period jitter -
» [SI-LIST] Re: Phase jitter vs. period jitter -
» [SI-LIST] SATA Cable Assembly Models -
» [SI-LIST] Re: Phase jitter vs. period jitter -
» [SI-LIST] Re: PCB impedance coupon measurement -
» [SI-LIST] Re: Phase jitter vs. period jitter -
» [SI-LIST] Re: Return current -
» [SI-LIST] Re: PCB impedance coupon measurement -
» [SI-LIST] Re: Reflection due to far end capacitor -
» [SI-LIST] Re: PCB impedance coupon measurement -
» [SI-LIST] Re: PCB impedance coupon measurement -
» [SI-LIST] 回复： DDR-simulation -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] Re: DC resistance measurement -
» [SI-LIST] DC resistance measurement -
» [SI-LIST] DDR-simulation -
» [SI-LIST] Re: hspice convergence problem -
» [SI-LIST] Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Hot Jobs @ Intel -
» [SI-LIST] Re: hspice convergence problem -
» [SI-LIST] Re: DDR logic threshold -
» [SI-LIST] Re: PCB impedance coupon measurement -
» [SI-LIST] Re: hspice convergence problem -
» [SI-LIST] Re: DDR logic threshold -
» [SI-LIST] hspice convergence problem -
» [SI-LIST] DDR logic threshold -
» [SI-LIST] 30 minute podcast from IEEE EMC Symposium -
» [SI-LIST] PCB impedance coupon measurement -
» [SI-LIST] Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: High power shunt (~5A) -
» [SI-LIST] High power shunt (~5A) -
» [SI-LIST] Re: IBM Alphaworks Program -
» [SI-LIST] Re: IBM Alphaworks Program -
» [SI-LIST] IBM Alphaworks Program -
» [SI-LIST] Re: measuring switching thersholds -
» [SI-LIST] Re: measuring switching thersholds -
» [SI-LIST] Re: Reflection due to far end capacitor -
» [SI-LIST] Reflection due to far end capacitor -
» [SI-LIST] Re: measuring switching thersholds -
» [SI-LIST] Re: Reflection on differential termination -
» [SI-LIST] measuring switching thersholds -
» [SI-LIST] Reflection on differential termination [correction] -
» [SI-LIST] Reflection on differential termination -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Return current -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: 回复： Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Asian IBIS Summit (China) Second Announcement -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Minimally invasive monitoring -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] 回复： Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: Cable grounding scheme -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: May I know how can I check the ibis model from vendor -
» [SI-LIST] May I know how can I check the ibis model from vendor -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Cable grounding scheme -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Setup-Hold Equations for Source Synchronous Design -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] 回复： Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Re: How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] How to compensate the result if the flight time is a negative value?Thanks! -
» [SI-LIST] Minimally invasive monitoring -
» [SI-LIST] Re: 4 month Signal Integrity Contract at Intel in Santa Clara, CA -
» [SI-LIST] Frequency-dependent transmission line in PSpice? -
» [SI-LIST] 4 month Signal Integrity Contract at Intel in Santa Clara, CA -
» [SI-LIST] Asian IBIS Summit (Japan) First Announcement -
» [SI-LIST] Signal Integrity Opportunity in San Jose -
» [SI-LIST] R: Re: R: Re: Wire bonding -
» [SI-LIST] Re: R: Re: Wire bonding -
» [SI-LIST] Re: R: Re: Wire bonding -
» [SI-LIST] Re: R: Re: Wire bonding -
» [SI-LIST] R: Re: Wire bonding -
» [SI-LIST] Re: Wire bonding -
» [SI-LIST] Re: SATA thru Board-to-Board Connector -
» [SI-LIST] Re: SATA thru Board-to-Board Connector -
» [SI-LIST] Re: SATA thru Board-to-Board Connector -
» [SI-LIST] SATA thru Board-to-Board Connector -
» [SI-LIST] R: Wire bonding -
» [SI-LIST] Re: Wire bonding -
» [SI-LIST] Wire bonding -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] FW: High Speed SI Support Position at Mentor Graphics -
» [SI-LIST] Re: SSN analysis? -
» [SI-LIST] Re: SSN analysis? -
» [SI-LIST] Re: SSN analysis? -
» [SI-LIST] SSN analysis? -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] Re: DDRAM BUS Testing -
» [SI-LIST] DDRAM BUS Testing -
» [SI-LIST] Re: Circuit for differential to single end conversion -
» [SI-LIST] Re: Circuit for differential to single end conversion -
» [SI-LIST] Circuit for differential to single end conversion -
» [SI-LIST] Re: eye diagram in awaves -
» [SI-LIST] Re: eye diagram in awaves -
» [SI-LIST] eye diagram in awaves -
» [SI-LIST] Locating "hot" grounds -
» [SI-LIST] Asian IBIS Summit (China) First Announcement -
» [SI-LIST] Re: Ansoft SIwave vs. Cadence Allegro -
» [SI-LIST] Ansoft SIwave vs. Cadence Allegro -
» [SI-LIST] Michael W Wielebski/Mequon/RA/Rockwell is out of the office. -