Charles, You have a very valid point. I'm surprised at some guidelines concerning the noise measurements right across the decoupling cap pads. Those are the places you'd possibly observe the lowest noise on a PCB. Move a few inches away and the noise will peak orders of magnitude -in a cap-free zone. For a true representation, the measurement should be taken at the Vdd pin of the device. It goes without saying a cap at this point is the best bet. Regards Ihsan On 8/3/06, Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx> wrote: > > Hi Mike=20 > > One thing that has vexed me in the past ( and continues > to vex me actually ) is the measurement of noise at the > decoupling cap. If the cap is some distance from the > chip - the the noise seen at the cap will not faithfully > represent the noise at the chip.=20 > > I'd like to ask you (and the folks on the reflector) > your opinion on the "best" location for measuring and qualifying > power noise. > > Thanks!! > =20 > > Best Regards > Charles Grasso > Compliance Engineer > Echostar Communications Corp. > Tel: 303-706-5467 > Fax: 303-799-6222 > Cell: 303-204-2974 > Pager/Short Message: 3032042974@xxxxxxxxx > Email: charles.grasso@xxxxxxxxxxxx; > Email Alternate: chasgrasso@xxxxxxxx > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of Michael Rose > Sent: Wednesday, August 02, 2006 5:07 PM > To: Edi.Fraiman@xxxxxxxxxx; Vinu Arumugham; si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: DDRAM BUS Testing > > Edi, > > I assume you're worried about signal integrity (not =3D > logic/functionality). Some troubleshooting tips to try: > > 1. measure noise on the Vref lines for both the FPGA and memory. I don't > =3D > remember offhand but I belieive max is around 30mV. Micron Tech has a = > =3D > good DDR layout guide. > > 2. carefully measure 1.8V or 2.5V Vcc and Vtt noise (use an AC-coupled = > =3D > 50 ohm coax soldered directly to a local bypass cap site. > > 3. Tie a probe to the DDR clock at the memory to trigger a high-speed = > =3D > scope (> 4GHz). It's nice to have software write a test loop to generate > =3D > various read and write bit patterns on the memory bus (especially =3D > alternating 00s and FFs). Probe each memory line and note under/over =3D > shoot, jitter, Tsu and Th. Remember you have to probe D/DQ at the memory > =3D > for write data and at the FPGA for read data. > > 4. For Xilinx FPGAs, pay particular attention to undershoot (see their = > =3D > appnote where they suggest running the memory bus drivers at .3V below = > =3D > Vcc to prevent reverse biasing the clamps). > > I bet you'll find either excessive power supply noise, Vref noise, Vtt = > =3D > noise, or under/over shoot > > Good Luck, Mike > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Fraiman, Edi > Sent: Wednesday, August 02, 2006 4:01 PM > To: Vinu Arumugham; si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: DDRAM BUS Testing > > > Yes, FPGA support JTAG. > But JTAG frequency is low. JTAG test wasn't working because we are out > of spec (minimum DDR operating frequency). > > =3D3D20 > Best regards, > =3D3D20 > Edi Fraiman > > > > -----Original Message----- > > From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]=3D3D20 > > Sent: Wednesday, August 02, 2006 3:54 PM > > To: Fraiman, Edi > > Subject: Re: [SI-LIST] DDRAM BUS Testing > >=3D3D20 > >=3D3D20 > > The FPGA does not support JTAG? > >=3D3D20 > > Thanks, > > Vinu > >=3D3D20 > > Fraiman, Edi wrote: > >=3D3D20 > > >Hi, > > >=3D3D20 > > > > > >I'm working on a design that includes FPGA with DDRAM controller =3D > and=3D3D20 > > >several DDRAM chips. The traces goings direct from FPGA to=3D3D20 > > DDRAM with=3D3D20 > > >necessary pulll up resistor to Vref. (SSTL interface)=3D3D20 > > without any debug=3D3D20 > > >connector. > > > > > >=3D3D20 > > > > > >Sometimes we have productions problems. It is very difficult to =3D > find=3D3D20 > > >what bit in bus between FPGA and DDRAM is shorted or disconnected. > > > > > >Could somebody give any tips how it's possible debug DDRAM busses =3D > in=3D3D20 > > >terms of production issues. > > > > > >=3D3D20 > > >=3D3D20 > > >Best regards, > > >=3D3D20 > > >Edi Fraiman > > >=3D3D20 > > > > > > > > > - - - - - Appended by Scientific Atlanta, a Cisco=3D3D20 > > company - - - -=3D3D20 > > >- > > >This e-mail and any attachments may contain information=3D3D20 > > which is confidential, proprietary, privileged or otherwise=3D3D20 > > protected by law. The information is solely intended for the=3D3D20 > > named addressee (or a person responsible for delivering it to=3D3D20 > > the addressee). If you are not the intended recipient of this=3D3D20 > > message, you are not authorized to read, print, retain, copy=3D3D20 > > or disseminate this message or any part of it. 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