[SI-LIST] Re: DDRAM BUS Testing

Jim, S. M. Electronics sells 5kHz-23GHz 100V DC blocks that are great 
for most PDN work for about $50. a pop, SD3238, SD3238B.  Those let 
you pretty much see everything accurately except low frequency 
resonances between the regulator control loop and the bulk caps.

Thanks for the report.  It was interesting.  When you look at the 
measured noise sensitivity versus capacitor count in the various 
tested configurations, it speaks strongly to being interconnect 
inductance limited.

Regards,


Steve.


At 07:19 PM 8/6/2006, Jim Antonellis wrote:

>Hi Larry,
>
>Hope all is well.
>
>This is exactly the measurement setup I have settled into over the
>last couple of years. To the others who may try this method for the
>first time, don't forget to dial in the correct DC offset on your
>scope so you can get a good amount of vertical gain on the AC noise
>component, and, if you MUST AC couple (due to an unusually high DC
>offset that the scope can not dial out), note that you have now
>introduced a high-pass RC filter with your capacitor and the 50-ohm
>scope termination so you will be missing the lower frequency components
>(which may or may not matter in your app).
>
>Jim
>
>
>-
>Jim Antonellis   janton@xxxxxxxxxxxx
>Broadcom Corp    www.broadcom.com
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>Cell: 978.618.4745
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>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Larry Smith
>Sent: Friday, August 04, 2006 1:49 PM
>To: weirsi@xxxxxxxxxx; Charles.Grasso@xxxxxxxxxxxx; mrose@xxxxxxxxxxxx;
>Edi.Fraiman@xxxxxxxxxx; Vinu Arumugham; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDRAM BUS Testing
>
>Steve has some really good comments below about power distribution systems
>and techniques for measurement.  I wanted to add a few comments.
>
>You must remove the decoupling capacitor from pads that you use to measure
>the PDS.  I was burned by this many years ago...  If you leave the cap on
>the pads and probe the top of the cap, you are looking at very "colored"
>noise.  The decoupling capacitor mounted on the pads resonates at some
>series resonant frequency.  The voltage at the probable part of the
>capacitor is maximized at that frequency.  If the cap is effectively doing
>it's job, you will see huge noise at this frequency.  Take the cap off the
>pad before making the measurement.
>
>Second, there are usually multiple capacitors connected to the power planes,
>almost always more than 10 and often more than 100.  Removal of one
>capacitor has minimal impact.  The planes are pretty low impedance
>(inductance) compared to the mounting inductance of the decoupling
>capacitor.  If they are not, then we have not connected the caps in
>parallel.  At high frequency, the inductance of all the capacitors in
>parallel should be compared to the spreading inductance of the power planes
>that transport the current from the caps to the load.  When the inductance
>of the planes exceeds the inductance of the parallel caps, there is no point
>in putting any more caps on the board because the PDS is power plane
>limited.  Power planes can generally support between 10 and 200 decoupling
>capacitors depending on the dielectric thickness and the mounting inductance
>of the caps.  Removal of one of these caps, preferably close to the load,
>will not significantly change the voltage on the planes or the quality of
>power observed at the load.
>
>Third, the best way that I have found to measure noise on the PCB power
>planes is at the vias directly under the surface mount BGA.  In almost all
>cases there will be through hole vias available on the backside of the
>board.  Use a hot soldering iron to raise up a little cone of solder above
>the via for power and ground vias that are reasonably close to each other.
>Then do a little creative work with your exacto knife on some small diameter
>50 Ohm coax cable and solder attach the cable to the power and ground vias.
>This method presents a very small measurement loop.  The 50 Ohm impedance of
>the coax is very high compared to the PDS that is being measured (at least
>it better be, otherwise we are in real trouble), and it is a very high
>bandwidth probe.  This is a delicate connection and you will have to provide
>strain relief with kapton tape, wire ties and by any other means possible.
>It gets you as close to the PDS as possible right under the BGA and does not
>involve the removal of any decoupling capacitors.
>
>Another advantage of this technique is that it is inside the spreading
>inductance of the PCB power planes.  If your PDS is power plane limited, you
>will begin to see the effects of the chip capacitance resonating with the
>total mounting inductance from this measurement point.  As Steve mentions,
>the only thing you can do better than this (for core
>power) is to have a differential pair of non-current carrying power and
>ground balls connected directly into the package or die.
>
>Regards,
>Larry Smith
>Altera Corporation
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Thursday, August 03, 2006 5:00 PM
>To: Charles.Grasso@xxxxxxxxxxxx; mrose@xxxxxxxxxxxx; Edi.Fraiman@xxxxxxxxxx;
>Vinu Arumugham; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDRAM BUS Testing
>
>Charles, 5% noise tolerance spec at the planes or caps will someday=20 go
>the route of the infamous 50pF TTL load spec.  It tells us only a=20 little
>bit about what we really want to know, and that is what is=20 happening at
>the die.  The value of looking at a capacitor site or=20 even a dedicated
>probe into the planes depends on what you want to know.
>
>First, even if the cap is very close to the chip, that location still=20
>tells you about power distribution near that locale.  Even if the cap=20 is
>right next to the IC connected through thin planes, or on the=20 backside of
>the PCB, once we take the Z axis wild ride up into the=20 chip package, the
>results can be very different.  For example we can=20 have dead quiet PCB
>planes and but dangerously noisy internal rails=20 at the die.  When Lee
>Ritchey complains about effects attributed to=20 packages, that is the sort
>of symptom to watch out for:  quiet PCB=20 but horribly noisy die.  All that
>interconnect from the die out works=20 with the planes and bypass cap
>network to form a low pass filter than=20 disguises what is happening at the
>die.
>
>If you want to know how much noise from a given IC is propagating out=20 the
>planes, then you can sample the planes.  Removing a capacitor and=20 probing
>that site differentially provides a pretty good picture of=20 what the
>planes see in that locale.  As much as we would like to=20 think of the
>planes as bedrocks of stability, they are far more=20 volatile.  In
>applications like yours where bypass caps have to do a=20 higher proportion
>of the work than in boards with many layers, the=20 value of that
>information is limited.
>
>If you want to know power supply noise across Vdd/Vss at the chip you=20
>really need to have a diff pair of Vdd/Vss from the die=20 available.  With
>core supplies you have no choice but to burn a=20 Vdd/Vss pair.  A pair of
>outputs is not a bad substitute for looking=20 at noise on an I/O rail.
>
>As Mark pointed out, the signals that you bring out are subject to=20 cross
>talk from whatever is near them in the package and the PCB.  It=20 doesn't
>matter what kind of signals they are.
>
>If you want to see what the ambient is for a given receiver, then you=20
>need to bring out that signal line and its Vref differentially.  That=20 can
>be very difficult as Vref is often short changed pin-wise.
>
>Regards,
>
>Steve.
>At 12:52 PM 8/3/2006, Grasso, Charles wrote:
> >Hi Mike=3D20
> >
> >One thing that has vexed me in the past ( and continues to vex me
> >actually ) is the measurement of noise at the decoupling cap. If the
> >cap is some distance from the chip - the the noise seen at the cap will
> >not faithfully represent the noise at the chip.=3D20
> >
> >I'd like to ask you (and the folks on the reflector) your opinion on
> >the "best" location for measuring and qualifying power noise.
> >
> >Thanks!!
> >=3D20
> >
> >Best Regards
> >Charles Grasso
> >Compliance Engineer
> >Echostar Communications Corp.
> >Tel: 303-706-5467
> >Fax: 303-799-6222
> >Cell: 303-204-2974
> >Pager/Short Message: 3032042974@xxxxxxxxx
> >Email: charles.grasso@xxxxxxxxxxxx;
> >Email Alternate: chasgrasso@xxxxxxxx
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
> >On Behalf Of Michael Rose
> >Sent: Wednesday, August 02, 2006 5:07 PM
> >To: Edi.Fraiman@xxxxxxxxxx; Vinu Arumugham; si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: DDRAM BUS Testing
> >
> >Edi,
> >
> >I assume you're worried about signal integrity (not =3D3D
> >logic/functionality). Some troubleshooting tips to try:
> >
> >1. measure noise on the Vref lines for both the FPGA and memory. I
>don't
> >=3D3D
> >remember offhand but I belieive max is around 30mV. Micron Tech has a =
>=3D
> >=3D3D
> >good DDR layout guide.
> >
> >2. carefully measure 1.8V or 2.5V Vcc and Vtt noise (use an AC-coupled
>=3D
> >=3D3D
> >50 ohm coax soldered directly to a local bypass cap site.
> >
> >3. Tie a probe to the DDR clock at the memory to trigger a high-speed =
>=3D
> >=3D3D
> >scope (> 4GHz). It's nice to have software write a test loop to
>generate
> >=3D3D
> >various read and write bit patterns on the memory bus (especially =3D3D
> >alternating 00s and FFs). Probe each memory line and note under/over
>=3D3D
> >shoot, jitter, Tsu and Th. Remember you have to probe D/DQ at the
>memory
> >=3D3D
> >for write data and at the FPGA for read data.
> >
> >4. For Xilinx FPGAs, pay particular attention to undershoot (see their
>=3D
> >=3D3D
> >appnote where they suggest running the memory bus drivers at .3V below
>=3D
> >=3D3D
> >Vcc to prevent reverse biasing the clamps).
> >
> >I bet you'll find either excessive power supply noise, Vref noise, Vtt
>=3D
> >=3D3D
> >noise, or under/over shoot
> >
> >Good Luck, Mike
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Fraiman, Edi
> >Sent: Wednesday, August 02, 2006 4:01 PM
> >To: Vinu Arumugham; si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: DDRAM BUS Testing
> >
> >
> >Yes, FPGA support JTAG.
> >But JTAG frequency is low. JTAG test wasn't working because we are out
> >of spec (minimum DDR operating frequency).
> >
> >=3D3D3D20
> >Best regards,
> >=3D3D3D20
> >Edi Fraiman
> >
> >
> > > -----Original Message-----
> > > From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]=3D3D3D20
> > > Sent: Wednesday, August 02, 2006 3:54 PM
> > > To: Fraiman, Edi
> > > Subject: Re: [SI-LIST] DDRAM BUS Testing =3D3D3D20 =3D3D3D20  The
> > >FPGA does not support JTAG?
> > >=3D3D3D20
> > > Thanks,
> > > Vinu
> > >=3D3D3D20
> > > Fraiman, Edi wrote:
> > >=3D3D3D20
> > > >Hi,
> > > >=3D3D3D20
> > > >
> > > >I'm working on a design that includes FPGA with DDRAM controller
>=3D3D
> >and=3D3D3D20
> > > >several DDRAM chips. The traces goings direct from FPGA to=3D3D3D20
> > > DDRAM with=3D3D3D20
> > > >necessary pulll up resistor to Vref. (SSTL interface)=3D3D3D20
> > > without any debug=3D3D3D20
> > > >connector.
> > > >
> > > >=3D3D3D20
> > > >
> > > >Sometimes we have productions problems. It is very difficult to =
>=3D3D
> >find=3D3D3D20
> > > >what bit in bus between FPGA and DDRAM  is shorted or disconnected.
> > > >
> > > >Could somebody give any tips how it's possible debug DDRAM busses
>=3D3D
> >in=3D3D3D20
> > > >terms of production issues.
> > > >
> > > >=3D3D3D20
> > > >=3D3D3D20
> > > >Best regards,
> > > >=3D3D3D20
> > > >Edi Fraiman
> > > >=3D3D3D20
> > > >
> > > >
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