[SI-LIST] Re: flex circuit & chip scale basics
- From: "hreidmarkailen" <hreidmarkailen@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 Aug 2006 01:41:18 -0400
Markku,
Thanks very much.
I meant to say _wafer-scale_ I believe, where multiple small single-chip
pkgs are on a flex circuit. These have ultra-small footprint and what I
suppose you'd call "micro balls".
One question: the resistivity of the traces changes due to temperature,
and/or flexing? Is that correct? Also, I believe I read that the char.
impedance can change along a flex trace significantly. If so, is that a
function of being in the flexed (folded) position or having been flexed?
And if so, the dielectric properties change from mech. stress?
-----Original Message-----
From: Markku.Rouvala@xxxxxxxxx [mailto:Markku.Rouvala@xxxxxxxxx]
Sent: Monday, August 28, 2006 7:43 AM
To: hreidmarkailen@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] flex circuit & chip scale basics
Hi,
We have analyzed flexible circuit interconnections for high speed mobile
applications, which might be a little bit larger scale than chip scale,
but I would expect same phenomena to exist.
A couple of major issues to mention and to take care of are first:
typically problems with achieving 50ohm impedance controlled lines,
especially if talking about single-ended signaling and/or small
tolerances. Secondly, shielding and emission control from flex circuits
including crosstalk will need special care because of dynamic properties
of flexible circuit shield materials and the resistivity due to that.
We have modelled the flexible circuits with many tools, but perhaps the
most effective would be 2.5D-3D solvers and circuit level simulators
together - CST or Ansoft + HSPice or Aplac will do.
Best Regards, Markku Rouvala,
Senior Research Engineer
Computing Architectures Laboratory
Nokia Research Center
Helsinki / Finland
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of ext hreidmarkailen
>Sent: 25 August, 2006 09:29
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] flex circuit & chip scale basics
>
>Hello all,
>
>
>I'm interested in two main items regarding present
>understanding of modeling issues and actual DUT's SI
>performance (specific to flex/chip scale attach):
>
>
>
>1. flex circuit (miniature, for chip scale interconn.)
>
>2. chip scale SI
>
>
>
>Just the major issues are of interest, but detail is welcome.
>
>
>
>Possible issue examples:
>
>1. favored model generation approach for flex Tlines &
>attachment (ie:
>ADS vs. 3D solvers)
>2. xtalk factor due to small geometries in flex
>3. Impedance control
>4. Z changes vs. length due to materials properties, or
>other mech./SI
>interaction
>
>
>
>Regards
>
>hreidmarkailen
>
>
>
>
>
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